Semiconductor Device Segmentation for Product-Sum Error Reduction
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Solution Overview
Problem
The semiconductor device described in Patent Document 1 experiences increased errors due to high driving currents for data lines, which affects the accuracy of product-sum operations.
Innovation Solution
A semiconductor device configuration that divides input values into multiple bit values, uses memory units with ternary values to perform product-sum operations, and includes a sum operation circuit to reduce the driving current for data lines, thereby suppressing errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a large number of memory cells are connected to drive data lines for high-speed product-sum operations, then operation speed is improved, but driving current increases causing error rates to increase
Solution Approach 1:
The patent divides the cell array into multiple banks (first bank, second bank, third bank, fourth bank) and further segments memory cells into groups within each bank. This segmentation allows parallel operation across multiple banks while limiting the number of cells driving each individual data line, thereby maintaining high operation speed through parallelism while reducing error rates by controlling current per data line.
Solution Approach 2:
The patent introduces a bank dimension orthogonal to the traditional row-column memory cell organization. By adding this fourth dimension (bank level), the system achieves parallel processing across banks while maintaining manageable data line loading within each bank, effectively resolving the contradiction between speed and reliability.
2Productivity
If memory cells use ternary values for product-sum operations, then computational efficiency is improved, but operation accuracy decreases due to high driving current
Solution Approach 1:
By segmenting memory cells into groups across multiple banks, the patent enables ternary value product-sum operations to proceed in parallel while limiting the current burden on each data line. This maintains computational efficiency through parallel ternary operations while improving accuracy by reducing current-induced errors in each operational unit.
3Productivity
If more memory cells are activated for parallel processing, then productivity is improved, but power consumption increases due to higher driving current requirements
Solution Approach 1:
The patent organizes memory cells into multiple banks that can operate in parallel, achieving high productivity through parallel processing. However, by limiting the number of cells per bank and controlling which cells are activated simultaneously within each bank, the system manages power consumption more effectively, preventing excessive current draw while maintaining parallel processing benefits.
Data Source
AI summary
A related-art semiconductor device has a problem that is a large operation error. A semiconductor device according to an embodiment includes: an input control circuit dividing a plurality of bit values representing an input value into a plurality of division values each having a predetermined number of bits, and outputting the division values; a plurality of memory units each including a plurality of memory cells each outputting a product of a held value represented by a ternary value and any one of the plurality of bit values representing the input value, each of the plurality of memory units corresponding to any one of the division values; and a sum operation circuit performing sum operation processing to an output value to be output for each of the division values, and outputting a final operation result value.