3D Stacked Semiconductor Structure with Segmented Gate Control
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Solution Overview
Problem
Current memory devices face challenges in achieving high element density and low manufacturing costs while maintaining reliability and process stability, particularly in three-dimensional integrated circuit memory with small memory elements and improved process windows.
Innovation Solution
A semiconductor structure and manufacturing method involving alternately stacked semiconductor and insulating layers, with specific geometries and conductive features to form reliable and compact memory elements, including a first stacked structure with perpendicular portions and conductive islands, and a second stacked structure with parallel and perpendicular portions, allowing for efficient patterning and dielectric element formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional 3D stack memory device methods are used, then memory capacity can be increased, but manufacturing cost per cell increases and process stability deteriorates
Solution Approach 1:
The memory device is divided into multiple independent stacked structures, each containing separate memory cell strings with gate structures. This segmentation allows each stack to be manufactured and processed independently, improving process stability and reducing the impact of defects on overall device performance, thereby lowering the effective cost per cell.
Solution Approach 2:
Different regions of the stacked structure are designed with different properties - specifically, neighboring stacks have isolated gate structures with different potentials in different regions. This local differentiation improves reliability and process window while maintaining high density, as each region can be optimized for its specific function without affecting the entire device.
2Quantity of substance
If memory element size is decreased to increase density, then element density improves, but reliability and process window deteriorate
Solution Approach 1:
The patent transitions from planar memory structures to three-dimensional stacked structures with multiple layers extending in the vertical direction. This dimensional change allows high element density to be achieved without proportionally reducing the dimensions of individual memory elements, as density increases are achieved through added vertical layers rather than shrinking lateral features.
Solution Approach 2:
Memory cell strings are segmented into separate gate structures for neighboring stacks, with each gate structure having independent potential control. This segmentation isolates process variations and reliability issues to specific stacks, preventing defects from propagating across the entire device, thereby maintaining reliability even as density increases.
3Device complexity
If neighboring stacks share common source/drain regions, then manufacturing complexity is reduced, but process window and reliability deteriorate
Solution Approach 1:
Source and drain regions are segmented into separate regions for each stack, with isolated gate structures controlling each stack independently. While this increases structural complexity, it significantly improves the process window and reliability by preventing process variations in one stack from affecting neighboring stacks, allowing each stack to be optimized independently.
Solution Approach 2:
Each stack is designed with locally optimized source/drain regions and gate structures tailored to specific performance requirements. This local quality approach allows different stacks to have different characteristics optimized for their specific functions, improving overall device reliability and process window despite the increased manufacturing complexity.
Data Source
AI summary
A semiconductor structure is provided. The semiconductor structure includes a first stacked structure. The first stacked structure includes a first stacked portion disposed along a first direction, at least one second stacked portion connected with the first stacked portion and disposed along a second direction perpendicular to the first direction, and at least one third stacked portion connected with the first direction and arranged alternately with the second stacked portion along the first direction. The width of the third stacked portion is smaller than the width of the second stacked portion along the second direction.