Semiconductor Device With Segmented Trench and Planar Gate Layers
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Solution Overview
Problem
Power semiconductor devices require high breakdown voltage, high current, and high-speed switching characteristics while minimizing power loss, which existing designs struggle to achieve effectively by optimizing the epi region concentration and thickness to manage the surface electric field and reverse bias PN junction structure.
Innovation Solution
A semiconductor device design combining trench gate and planar gate structures, with alternating first and second gate layers of different depths and widths, positioned between P regions and N+ regions, to increase channel density and improve current density by forming additional vertical channels and distributing electric fields effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a conventional planar gate structure is used, then the device structure is simple, but the channel density is limited and current density is insufficient
Solution Approach 1:
The gate structure is segmented into multiple gate layers (first gate layer and second gate layer) with different depths and widths, creating multiple independent channel regions. This segmentation increases the total channel density and current carrying capacity while maintaining manageable structural complexity through modular design
Solution Approach 2:
The invention transitions from a conventional single-plane gate structure to a multi-dimensional gate architecture with gates at different depths (first gate layer at deeper level, second gate layer at shallower level) and different widths. This dimensional expansion creates additional vertical channels and increases effective channel area, thereby improving current density
2Reliability
If the epi region concentration and thickness are optimized for breakdown voltage, then the reverse bias characteristic is improved, but the forward current density is limited
Solution Approach 1:
The channel region is segmented into multiple independent channels created by the first and second gate layers at different depths. This segmentation allows the device to maintain the epi region concentration and thickness optimized for breakdown voltage while providing multiple parallel current paths that increase forward current density
Solution Approach 2:
By introducing vertical dimensionality with gate layers at different depths, the invention creates additional current conduction paths without changing the horizontal epi region dimensions that determine breakdown voltage. This enables simultaneous optimization of both reverse bias reliability and forward current density
3Productivity
If a single gate layer is used, then the manufacturing process is simpler, but the channel density and current flow capacity are insufficient
Solution Approach 1:
The gate structure is divided into multiple gate layers with distinct functions and positions. The first gate layer creates channels at a deeper level while the second gate layer creates channels at a shallower level, effectively segmenting the current flow paths and increasing total channel density
Solution Approach 2:
The gate layers are nested vertically within the semiconductor structure, with the first gate layer positioned at a deeper level and the second gate layer positioned at a shallower level. This nested arrangement maximizes space utilization and creates multiple channel regions without excessive horizontal expansion
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design enhances current density by increasing channel density and reducing resistance, allowing for higher current flow without passing through JFET regions, thus improving the semiconductor device's performance in terms of breakdown voltage and power loss reduction.
Implementation Method 1
A channel may be formed in a surface of the third P region facing the first gate layer, and a channel may be formed in a surface of the fourth P region facing the first gate layer
Implementation Method 2
a first gate layer positioned between a protruded third P region among the first P region and a protruded fourth P region among the second P region, and a second gate layer positioned between the first N+ region and the second N+ region
Data Source
AI summary
An exemplary semiconductor device may include a substrate, an N− epitaxial layer positioned on the substrate, a first P region and a second P region positioned apart from each other on the N− epitaxial layer, a first N+ region positioned within the first P region, a second N+ region positioned within the second P region, and a gate layer positioned between the first P region and the second P region.