Semiconductor Device With Segmented Gate Structures
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Solution Overview
Problem
As ultra-high voltage semiconductor devices scale down, it becomes challenging to achieve high breakdown voltage, low specific on-resistance, and high reliability in both room temperature and high temperature environments.
Innovation Solution
The semiconductor device design includes a substrate with a high-voltage well and doped regions, along with multiple gate structures and drain/source regions, which are strategically positioned and manufactured using specific doping and oxidation processes to enhance breakdown voltage and reduce specific on-resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If device dimensions are scaled down, then device size is reduced, but breakdown voltage decreases and reliability deteriorates
Solution Approach 1:
The device divides the channel into multiple segments with separate gate structures (first gate structure and second gate structure) controlling different regions. This segmentation allows independent optimization of each region's electrical characteristics, enabling the smaller device to maintain high breakdown voltage through localized field control while keeping overall dimensions reduced.
Solution Approach 2:
Different regions of the device are doped with different conductivity types and concentrations (first conductivity type in substrate, second conductivity type in well, first conductivity type in doped region). This local quality variation creates optimized electrical fields in specific areas, allowing the scaled-down device to achieve high breakdown voltage through localized field management rather than relying on overall device size.
2Volume of moving object
If device dimensions are scaled down, then device size is reduced, but specific on-resistance increases
Solution Approach 1:
The channel is segmented into multiple regions controlled by separate gate structures, allowing each segment to be optimized for low resistance. The first and second gate structures can be independently biased to minimize on-resistance in their respective regions, enabling the compact device to achieve low specific on-resistance without increasing overall device size.
Solution Approach 2:
The device employs multiple doping concentrations and conductivity types in different regions (substrate, well, doped region) to optimize the electrical parameters. By carefully controlling doping parameters in each segmented region, the device achieves low specific on-resistance in the scaled-down structure through parameter optimization rather than size increase.
3Volume of moving object
If device dimensions are scaled down, then device size is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The device structure is segmented into distinct regions (substrate, well, doped region) with separate gate structures. This segmentation allows each component to be formed and positioned independently using standard fabrication techniques, reducing the cumulative precision requirements compared to forming a single integrated structure. Each segmented component can be manufactured with conventional precision tolerances.
Solution Approach 2:
The device employs preliminary doping actions to establish the substrate, well, and doped region with specific conductivity types before forming the gate structures. This preliminary action creates a pre-configured electrical landscape that guides subsequent gate formation and alignment, reducing the precision requirements for final gate positioning by establishing reference structures in advance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves a 9% higher drain current and 9% lower specific on-resistance compared to comparative examples, maintaining similar breakdown characteristics and reliability across varying temperatures.
Implementation Method 1
forming a high-voltage well having a second conductivity type in the substrate, forming a high-voltage doped region having the first conductivity type in the high-voltage well
Implementation Method 2
a source region disposed in the high-voltage doped region, a drain region disposed in the high-voltage well and spaced apart from the high-voltage doped region
Data Source
AI summary
A semiconductor device includes a substrate having a first conductivity type, a high-voltage well having a second conductivity type and disposed in the substrate, a high-voltage doped region having the first conductivity type and disposed in the high-voltage well, a drain region disposed in the high-voltage well and spaced apart from the high-voltage doped region, a source region disposed in the high-voltage doped region, a first gate structure disposed above a first side portion of the high-voltage doped region between the source region and the drain region, and a second gate structure disposed above a second and opposite side portion of the high-voltage doped region.