Semiconductor Device Structures With Segmented Passivation Layers
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Solution Overview
Problem
Current semiconductor devices face issues with high resistance drift in thin film resistors due to mechanical stress from the back-end-of-line (BEOL) process, leading to a piezoresistance effect that affects the accuracy and reliability of these devices.
Innovation Solution
The semiconductor device structure incorporates a top metal layer with specific portions and a passivation layer having a hollowed pattern to alleviate anisotropic stresses, which reduces the piezoresistance effect and minimizes the drift rate of resistance values in thin film resistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional continuous passivation layer is used, then the device structure is simple and easy to manufacture, but mechanical stress causes high resistance drift in thin film resistors
Solution Approach 1:
The passivation layer is divided into separate first and second portions with a gap between them, allowing stress relief while maintaining device functionality. This segmentation reduces the mechanical stress transmitted to the thin film resistors, thereby reducing resistance drift from greater than 10% to less than 5%.
Solution Approach 2:
The gap in the passivation layer is strategically positioned to expose specific portions of the top metal layer where stress relief is most needed. This local modification allows stress relief in critical areas while maintaining coverage and protection in other areas, optimizing the balance between stress reduction and device protection.
2Object-affected harmful factors
If the passivation layer completely covers the top metal layer, then the metal layer is protected, but stress from the passivation layer increases piezoresistance effect
Solution Approach 1:
A gap is introduced in the passivation layer to extract or remove the stress-inducing portion of the continuous passivation structure. This gap allows the passivation layer to fulfill its protective function while eliminating the harmful mechanical stress that causes piezoresistance effect and resistance drift in the thin film resistors.
3Manufacturing precision
If a hollowed pattern passivation layer is used, then stress is relieved and resistance drift is reduced, but the manufacturing process becomes more complex
Solution Approach 1:
The passivation layer is fabricated as segmented first and second portions with a gap between them. This segmentation approach, while adding design complexity, can be implemented using standard photolithography and deposition processes, making the manufacturing complexity manageable while achieving significant improvements in resistance value accuracy (reducing drift to less than 5%).
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed structure effectively reduces the drift rate of resistance values in thin film resistors to less than 5%, compared to conventional devices which experience drift rates greater than 10%, thereby enhancing the accuracy and reliability of semiconductor devices.
Implementation Method 1
Mechanical stress is one of the main causes of resistance drift. For example, in the back-end-of-line (BEOL) process for manufacturing semiconductor devices, the stress from each process causes the resistors in the lower layer to generate a piezoresistance effect.
Data Source
AI summary
Semiconductor device structures are provided. The semiconductor device structures include a semiconductor substrate. The semiconductor device structures also include an inner metal layer disposed on the semiconductor substrate and a top metal layer disposed on the inner metal layer, wherein the top metal layer has a first portion and a second portion, and wherein the first portion completely covers the inner metal layer, the second portion surrounds the first portion, and the first portion is separated from the second portion. The semiconductor device structures further include a passivation layer disposed on the top metal layer, wherein the passivation layer has a hollowed pattern to expose the top metal layer.