Semiconductor Device With Segmented Source Drain Regions
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Solution Overview
Problem
Conventional Surrounding Gate Transistor (SGT) structures face challenges in achieving high integration and performance due to increased parasitic resistance, parasitic capacitance, and limited flexibility in circuit design, along with difficulties in forming gate lines with sufficient process margins.
Innovation Solution
A semiconductor device and production method that include a substrate with a dielectric film, featuring planar semiconductor layers and pillar-shaped semiconductor layers with silicide layers connecting drain and source regions, allowing for self-aligned gate electrode formation around pillar-shaped semiconductor layers, reducing parasitic resistance and capacitance, and enhancing area efficiency and circuit design flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional SGT structures are used to achieve high integration, then area efficiency is improved, but parasitic resistance increases
Solution Approach 1:
The source and drain regions are segmented into multiple regions (first source/drain regions and second source/drain regions) with different conductivity types arranged in an alternating pattern. This segmentation allows for optimized electrical characteristics while maintaining compact area, resolving the contradiction between area efficiency and parasitic resistance reduction.
2Area of stationary object
If conventional SGT structures are used to achieve high integration, then area efficiency is improved, but parasitic capacitance increases
Solution Approach 1:
The segmented source and drain regions with alternating conductivity types create isolated electrical zones that reduce parasitic capacitance coupling between adjacent regions, while still achieving high integration density through the compact pillar-shaped structure.
3Area of stationary object
If conventional SGT structures are used, then area efficiency is improved, but circuit design flexibility is limited
Solution Approach 1:
Different regions of the semiconductor device are assigned different conductivity types (n-type and p-type) in an alternating pattern, allowing local optimization of electrical characteristics. This enables versatile circuit design configurations while maintaining high area efficiency through the standardized pillar-shaped transistor structure.
4Ease of manufacture
If gate lines are formed with conventional methods, then manufacturing is simplified, but process margins are insufficient
Solution Approach 1:
The gate lines are formed using a preliminary patterning step where mandrels are first created, followed by conformal insulation film deposition and planarization. This preliminary structuring establishes precise geometric constraints that guide subsequent gate electrode formation, ensuring sufficient process margins while maintaining manufacturing simplicity.
Data Source
AI summary
It is intended to provide a semiconductor device comprising a circuit which has a connection between a drain region or a source region of a first MOS transistor and a drain region or a source region of a second MOS transistor. Each surround gate transistor (SGT) has a gate electrode that surrounds a sidewall of a pillar-shaped semiconductor layer.