Semiconductor Device With Segmented Trenches and Recessed Protection
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Solution Overview
Problem
Conventional semiconductor devices, such as planar MOS transistors and FinFETs, suffer from poor controlling ability over channel current and leakage issues due to inadequate trench structures and gate electrode formation processes.
Innovation Solution
A method for fabricating semiconductor devices involving the formation of trenches with varying widths, where a first gate dielectric layer and electrode are formed in a narrower trench, and a second gate dielectric layer and electrode in a wider trench, with recesses created between the electrodes and dielectric layers, and protection layers are applied to improve breakdown resistance and prevent leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional planar MOS transistor structures are used, then manufacturing is simple, but controlling ability on channel current is poor and leakage current is serious
Solution Approach 1:
The patent divides the gate structure into multiple segments with different trench widths. The first trench has a first width and the second trench has a second width different from the first, creating segmented gate electrodes that provide different controlling abilities in different regions. This segmentation allows improved channel current control while managing the complexity through a systematic multi-trench approach.
Solution Approach 2:
Different regions of the device are given different local qualities through varying trench widths. The first trench region and second trench region have different dimensions, creating local variations in gate control strength. This local quality differentiation enables optimized current control in specific areas without requiring complete restructuring of the entire device.
2Reliability
If FinFET structures are used, then multi-gate control is achieved, but device performance remains poor due to inadequate trench structures
Solution Approach 1:
The gate dielectric layer structure is segmented into first and second gate dielectric layers corresponding to the first and second trenches respectively. Each layer is formed with specific thickness and material properties suited to its region, enabling optimized device performance while managing structural complexity through systematic layering.
Solution Approach 2:
The patent applies local quality by forming different gate dielectric layer configurations in different trench regions. The first gate dielectric layer and second gate dielectric layer have different properties, providing locally optimized electrical characteristics for each region, thereby improving overall device performance without requiring uniform complex structures throughout.
3Reliability
If uniform trench widths are used, then manufacturing is simple, but leakage current control is inadequate
Solution Approach 1:
The trench structure is segmented into multiple trenches with different widths. The first trench and second trench have different width dimensions, allowing differentiated leakage control in different regions. This segmentation enables improved leakage current control while the trenches are formed in a systematic sequence that manages manufacturing complexity.
Solution Approach 2:
Different trench widths provide local quality variations for leakage control. The first trench width and second trench width are different, creating local differences in electrical characteristics that enable targeted leakage current management in specific device regions without requiring complete redesign of all trenches.
4Reliability
If gate electrodes are formed without recesses, then manufacturing is simpler, but breakdown resistance is poor
Solution Approach 1:
The gate electrode structure is segmented by forming recesses between the first gate electrode and second gate electrode. These recesses create distinct electrical zones that improve breakdown resistance by preventing direct electrical pathways between adjacent gates. The segmented structure manages complexity through systematic recess formation in the gate electrode layer.
Solution Approach 2:
Recesses are introduced at specific locations between gate electrodes to provide local quality enhancement for breakdown resistance. The recesses create localized electrical isolation zones without requiring complete restructuring of the entire gate electrode system, thereby improving reliability while managing structural complexity.
Data Source
AI summary
Semiconductor device is provided. The semiconductor device includes a base substrate and a first dielectric layer on the base substrate. The first dielectric layer contains a first trench and a second trench passing therethrough, and a width of the second trench is larger than a width of the first trench. The semiconductor device further includes a first gate dielectric layer and a first gate electrode in the first trench. A first recess is on the first gate dielectric layer between the first gate electrode and the first dielectric layer. The semiconductor device further includes a second gate dielectric layer and a second gate electrode in the second trench. A second recess is on the second gate dielectric layer between the second gate electrode and the first dielectric layer. The semiconductor device further includes a first protection layer in the first recess and a second protection layer in the second recess.