Semiconductor Device With Segmented Wells For Latch-Up And Size Trade-Off
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Solution Overview
Problem
Existing semiconductor devices struggle to independently design and optimize the impurity concentration and depth of wells for resistance elements and field effect transistors on a shared semiconductor substrate, leading to compromised latch-up characteristics and increased resistance element size.
Innovation Solution
A semiconductor device and manufacturing method where separate conductivity type wells are formed with distinct impurity concentrations and depths for resistance elements and transistors, allowing independent design of each well's profile, including forming n-type and p-type wells with specific impurity concentrations and depths to optimize resistivity and size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the impurity concentration of the well is reduced to increase resistivity in order to shrink the resistance element, then the resistance element size is reduced, but the latch-up characteristics are deteriorated
Solution Approach 1:
The invention divides the well structure into two independent parts: a first well for the resistance element and a second well for the field effect transistor. This segmentation allows each well to have independently optimized impurity concentrations, enabling the resistance element well to have high resistivity (low impurity concentration) for size reduction while the transistor well maintains appropriate impurity concentration for good latch-up characteristics.
Solution Approach 2:
The invention applies different impurity concentrations to different regions (wells) based on their specific functional requirements. The first well beneath the resistance element has a first impurity concentration optimized for high resistivity, while the second well for the transistor has a second impurity concentration optimized for device performance and latch-up prevention, allowing each region to have locally optimized properties.
2Reliability
If the impurity concentration of the well of the field effect transistor is increased and the resistivity is reduced, then the transistor performance is improved, but the resistance element size becomes larger
Solution Approach 1:
By segmenting the well structure into separate first and second wells, the invention allows the second well (for transistor) to have higher impurity concentration for improved transistor performance without affecting the first well (for resistance element), which maintains low impurity concentration and high resistivity for compact size.
Solution Approach 2:
The invention enables local optimization where the second well has high impurity concentration specifically where the transistor requires it for performance, while the first well maintains low impurity concentration where high resistivity is needed, allowing each region to have the quality it needs without compromising the other.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables improved latch-up characteristics and reduced size of resistance elements while maintaining prescribed resistivity, allowing for simultaneous shrinkage of the resistance element and enhancement of transistor performance.
Implementation Method 1
an insulating film formed in an upper layer portion of the semiconductor substrate
Implementation Method 2
a well formed immediately below the insulating film
Data Source
AI summary
A semiconductor device according to an embodiment includes: a semiconductor substrate; a resistance element of a first conductivity type formed in one region of the semiconductor substrate; a field effect transistor of a second conductivity type formed in another region of the semiconductor substrate; and a field effect transistor of the first conductivity type formed in still another region of the semiconductor substrate. The resistance element includes: an insulating film formed in an upper layer portion of the semiconductor substrate; and a well of the first conductivity type formed immediately below the insulating film, an impurity concentration at an arbitrary depth position in the well of the first conductivity is lower than an impurity concentration at the same depth position in a channel region of the field effect transistor of the second conductivity type.