Semiconductor Structure With Segmented Word Lines
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Solution Overview
Problem
The increasing parasitic capacitances between adjacent word lines in semiconductor structures degrade the electrical properties and performance of the semiconductor structure.
Innovation Solution
The method involves forming semiconductor channels in an array on a substrate, with bit lines and word lines extending along specific directions. Sub word lines are formed at intervals along one direction, and isolation structures are positioned between adjacent word lines and sub word lines to reduce parasitic capacitances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If word lines are arranged adjacently in the semiconductor structure, then the device complexity is reduced and manufacturing is simplified, but parasitic capacitances between adjacent word lines increase adversely affecting electrical properties
Solution Approach 1:
Each word line is divided into two separate sub-word lines that are positioned on opposite sides of the semiconductor channel. This segmentation increases the spacing between conductive elements of the same word line, thereby reducing parasitic capacitance while maintaining the functional integrity of the word line structure
Solution Approach 2:
The word lines are arranged in a three-dimensional configuration where sub-word lines are positioned on opposite sides of the channel along the first direction, rather than being stacked adjacent to each other in the same plane. This spatial redistribution across multiple dimensions reduces electromagnetic coupling and parasitic capacitance
2Productivity
If the spacing between adjacent word lines is reduced to increase storage density, then the productivity and storage capacity are improved, but parasitic capacitances between word lines increase degrading electrical properties
Solution Approach 1:
By segmenting each word line into two sub-word lines positioned on opposite sides of the channel, the effective spacing between conductive elements is increased even when word lines are densely packed. This allows higher storage density while controlling parasitic capacitance through the separated sub-line configuration
Solution Approach 2:
The isolation structures are selectively positioned between adjacent sub-word lines and between adjacent word lines at specific locations where parasitic capacitance would be most problematic. This localized isolation approach optimizes electrical properties without compromising overall storage density
Data Source
AI summary
Embodiments provide a method for fabricating a semiconductor structure and a structure thereof. The method includes: providing a substrate; forming, on the substrate, semiconductor channels arranged in an array along a first direction and a second direction; forming bit lines extending along the first direction, wherein the bit lines are positioned in the substrate, and each of the bit lines is electrically connected to the semiconductor channels arranged along the first direction; forming word lines extending along the second direction, wherein the word lines wrap part of side surfaces of the semiconductor channels arranged along the second direction, where one of the word lines includes two sub word lines arranged at intervals along the first direction, and the sub word lines cover part of opposite side surfaces of the semiconductor channels along the first direction; and forming isolation structures positioned between adjacent word lines and between adjacent sub word lines.