Semiconductor Select Gate Electrode Fabrication via Shared Conductive Layer
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Solution Overview
Problem
The production of semiconductor integrated circuit devices with independently controllable select gate electrodes requires an additional dedicated photomask process, increasing production costs due to the complex configuration of memory cells in a matrix layout.
Innovation Solution
A method that includes forming a memory circuit region with a memory gate structure between first and second select gate structures through a sidewall spacer, where the select gate electrodes are electrically separated by cutout portions, allowing for independent control without the need for an extra dedicated photomask process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a dedicated photomask process is used to fabricate independently controllable select gate electrodes in memory cells, then independent control of select gate electrodes is achieved, but production cost increases due to additional process steps
Solution Approach 1:
The patent combines the formation of select gate electrodes with the formation of word lines by using a single continuous conductive layer that serves dual purposes. The select gate electrodes are formed by selectively removing portions of this shared conductive layer, merging two fabrication processes into one and eliminating the need for a dedicated photomask process for select gates.
Solution Approach 2:
The conductive layer formed in the word line region is given multi-functionality by using it as the material source for both word lines and select gate electrodes. This universal conductive layer approach allows the same structural element to serve multiple circuit functions, reducing the number of separate fabrication processes required.
2Manufacturing precision
If additional photomask processes are added to produce complex memory cell structures, then manufacturing precision is improved, but production time increases
Solution Approach 1:
The patent performs preliminary action by forming the conductive layer for select gate electrodes at the same time as the word line conductive layer, before the actual select gate electrode formation is needed. This advance preparation of the conductive layer material eliminates the need for separate material deposition processes later, reducing overall production time while maintaining precision.
Solution Approach 2:
The patent merges the photomask processes for word lines and select gate electrodes into a single unified process. By combining these two patterning operations into one photomask step, the patent reduces the number of sequential process steps required, thereby decreasing total production time while achieving the necessary structural precision through the combined patterning.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces production costs by eliminating the need for an additional photomask process while maintaining independent control of the select gate electrodes, enhancing operational efficiency and reducing complexity in the semiconductor integrated circuit device fabrication.
Implementation Method 1
charge is injected into the charge storage layer by a quantum tunneling effect due to a voltage difference between the bit voltage and the memory gate voltage
Data Source
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AI summary
A method for producing semiconductor integrated circuit devices and a semiconductor integrated circuit device produced by the method are provided. In the method, when a first select gate electrode (G2a, G2b) and a second select gate electrode (G3a, G3b) that are independently controllable are formed in a production process, an extra dedicated photomask process for electrically separating the first select gate electrode (G2a, G2b) and the second select gate electrode (G3a, G3b) is not needed in addition to a conventional dedicated photomask process of fabricating a memory circuit region only, thereby achieving reduction in a production cost accordingly.