Semiconductor Device Select Gate GIDL Hole Generation
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Solution Overview
Problem
Current semiconductor devices face inefficiencies in erase operations due to insufficient hole generation during gate-induced drain leakage (GIDL) current, leading to data disturbance and increased bad blocks, especially as the number of erase and program operations increases.
Innovation Solution
A semiconductor device with a doped semiconductor layer and a channel pattern featuring a first and second semiconductor region of different materials, where the second semiconductor region has a lower energy band gap, enhances GIDL current generation by reducing the voltage required for the erase operation, thereby improving erase efficiency and reducing stress on select transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional single-material channel structure is used, then device structure is simple, but hole generation efficiency during erase operation is insufficient
Solution Approach 1:
The channel structure is divided into two semiconductor regions with different materials (first and second semiconductor regions) having different energy band gaps. The second semiconductor region with lower energy band gap is specifically positioned to enhance hole generation efficiency during erase operations, while the first semiconductor region maintains structural integrity. This local differentiation of material properties solves the contradiction by improving erase speed in the critical region without requiring complete restructuring of the entire channel.
Solution Approach 2:
The channel is constructed using composite semiconductor materials with different energy band gaps. The first semiconductor region uses a material with higher energy band gap, while the second semiconductor region uses a material with lower energy band gap. This composite structure enables enhanced hole generation efficiency during erase operations through the lower band gap material, directly addressing the insufficient hole generation problem while maintaining a manageable structural complexity.
2Reliability
If high voltage is applied to generate sufficient holes for erase operation, then hole generation is improved, but select transistor deterioration increases
Solution Approach 1:
The invention changes the energy band gap parameter of the semiconductor material in the second region to be lower than that of the first region. This parameter change enables more efficient hole generation at reduced voltage levels, as the lower band gap requires less energy to generate electron-hole pairs. Consequently, sufficient holes can be generated for reliable erase operations without applying excessive voltage that would cause select transistor deterioration.
3Duration of action of moving object
If multiple erase and program operations are performed, then device usage increases, but data disturbance and bad block formation increase
Solution Approach 1:
The second semiconductor region with lower energy band gap is specifically positioned to enhance hole generation efficiency during erase operations. This localized improvement in hole generation ensures that even after multiple program-erase cycles, sufficient holes can be generated to maintain data integrity and prevent data disturbance, thereby extending the device's operational life while maintaining reliability.
Solution Approach 2:
By changing the energy band gap parameter of the semiconductor material in the second region, the invention enables more efficient hole generation that persists through multiple operational cycles. This parameter modification ensures that hole generation efficiency is maintained even after repeated program and erase operations, preventing the accumulation of bad blocks and data disturbance that typically occur with extended device usage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively increases hole generation at lower voltages, enhancing erase operation speed and reliability, reducing data disturbance and bad block formation, and mitigating select transistor deterioration.
Implementation Method 1
The holes may be generated by a mechanism of generating gate induced drain leakage (GIDL) current using the select transistor
Data Source
AI summary
Provided herein is a semiconductor device and a method of manufacturing the same. The semiconductor device has improved erase characteristics by using a select gate enclosing a portion a first semiconductor region overlapping a second semiconductor region. The first semiconductor region and the second semiconductor region are formed of different semiconductor materials.