Semiconductor Select Line Separation via Wave-Shaped Trenches

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Solution Overview

Problem

Conventional semiconductor memory devices face challenges in efficiently forming select line separation layers without using dummy cell plugs, which affects space efficiency and operational reliability, especially when trying to pattern select line separation layers with small critical dimensions.

Innovation Solution

A method of manufacturing semiconductor devices that involves forming a select line separation trench with a wave shape along the contour of protruded sidewalls, filled with a non-conductor, eliminating the need for dummy plugs and allowing for precise control of critical dimensions and wave angles.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a separate dummy cell plug is disposed between cell plugs to form a drain select line separation layer, then the select line separation is achieved, but the space efficiency in the semiconductor memory device is reduced

Engineering Contradiction:
Improveselect line separationVSAvoidspace efficiency
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The invention extracts and eliminates the dummy cell plug from the structure by forming the select line separation layer directly between adjacent select lines through etching and filling processes, thereby achieving select line separation without occupying additional space between cell plugs

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The invention merges the select line separation layer formation with the existing select line structure by using the select lines themselves as boundaries, combining the separation function with the existing layout rather than adding a separate dummy structure

Inventive Principle:
Principle #5Merging (Combining)

2Area of stationary object

If a thin select line separation layer is directly inserted between adjacent select lines, then the space efficiency is improved, but the operational reliability cannot be secured because it is very difficult to pattern a select line separation layer having a desired critical dimension

Engineering Contradiction:
Improvespace efficiencyVSAvoidcritical dimension patterning
Core Design Contradiction:
Area of stationary objectVSManufacturing precision

Solution Approach 1:

The invention introduces a mandrel structure as an intermediary element that facilitates the formation of the select line separation layer. The mandrel serves as a temporary support and patterning guide, enabling precise critical dimension control during the etching and filling processes without requiring direct patterning of the separation layer itself

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The invention performs preliminary actions by forming the mandrel structure and conducting etching and filling operations before finalizing the select line separation layer. This preliminary patterning using the mandrel ensures that the critical dimensions are accurately established before the separation layer is fully formed

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11004862B2Semiconductor device and method of manufacturing the same
Publication Date: 2021.05.11 SK HYNIX INC
  • US11004862B2 patent drawing
  • US11004862B2 patent drawing
  • US11004862B2 patent drawing

AI summary

Provided herein may be a semiconductor device and a method of manufacturing the same. The method may include forming a second preliminary stack on a first preliminary stack; forming a first hard mask layer on the second preliminary stack; etching the first hard mask layer and forming holes through which the second preliminary stack is exposed; forming a second hard mask layer on the first hard mask layer to fill the holes; forming a linear trench by etching the second hard mask layer; forming a waved select line separation mask pattern by etching the exposed first hard mask layer; forming a select line separation trench by etching the exposed second preliminary stack using the select line separation mask pattern as an etching mask; and forming a select line separation layer by filling the select line separation trench with a non-conductor.