Semiconductor Device With Selection MIS-FETs For Nonvolatile Memory
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Solution Overview
Problem
The challenge lies in disposing nonvolatile memory cells in an array form within semiconductor chips containing main circuits without encountering issues such as data disturb, non-selection leaks, and misreading, which hinder efficient data storage and retrieval.
Innovation Solution
The integration of selection MIS-FETs electrically connected to nonvolatile memory cells, ensuring that write voltages are not applied to non-selected cells, preventing data disturb and leaks, and controlling read voltages to prevent unintended activation of non-selected MIS-FETs for reading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If nonvolatile memory cells are disposed in array form to reduce occupied area, then area efficiency is improved, but data disturb and non-selection leaks occur in non-selected cells
Solution Approach 1:
The patent divides the array of nonvolatile memory cells into individually selectable units by introducing selection MIS-FETs. Each memory cell or group of cells is equipped with its own selection transistor, allowing the array to be segmented into independently controllable segments. This enables selective access to only the desired memory cells while keeping others isolated, thereby preventing data disturb and non-selection leaks in non-selected cells while maintaining the compact array structure.
Solution Approach 2:
The selection MIS-FET acts as an intermediary element between the control circuitry and the nonvolatile memory cells. This intermediary component controls the electrical connection between the read/write circuitry and the memory cells, allowing selective activation of only the intended cells during operations. By introducing this intermediary switching mechanism, the patent prevents unwanted electrical interactions with non-selected cells, thus eliminating data disturb and non-selection leaks while preserving the area-efficient array configuration.
2Area of stationary object
If selection elements are added to enable array form disposal, then area efficiency is improved, but device complexity increases
Solution Approach 1:
The selection MIS-FETs are designed to serve multiple functions simultaneously: they act as switches for selective cell access, as isolation elements to prevent leaks, and as part of the overall memory cell structure. By making the selection elements multi-functional, the patent reduces the need for separate dedicated components for each function, thereby limiting the increase in device complexity while achieving the desired array configuration and data protection.
Data Source
AI summary
A semiconductor device includes a circuit forming area and a memory area including memory cells, first and second wells, a first conductor film formed over both wells and a second conductor film formed over the first well. First semiconductor regions are formed in the first region and a second semiconductor region is formed in the second region. The memory cells each include a capacitance element, including the first conductor film and second region, an element for reading data, including the first conductor film and first regions, and a selection field effect transistor, including the second conductor film and first regions. A length of the first conductor film of the capacitance element is larger than a length of the first conductor film of the element for reading data. A word line of the memory cell is connected to the second semiconductor region. During a reading data operation, a first bit line of the memory cell is connected to the first semiconductor region of the element for reading data via the selection field effect transistor.