Semiconductor Contact Filling With Selective ALD in High-Aspect Openings
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Solution Overview
Problem
Challenges arise in the semiconductor industry with the development of three-dimensional designs such as FinFETs and gate-all-around FETs due to issues in metal filling processes, particularly in forming conductive layers with high aspect ratios, which affect the integrity and performance of the devices.
Innovation Solution
A novel process involving atomic layer deposition (ALD) is used to form conductive layers with precise control, ensuring they adhere only to conductive surfaces and not dielectric layers, enhancing bottom coverage and process window, thereby improving the formation of conductive layers in high aspect ratio openings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional metal filling processes are used to form conductive layers in high aspect ratio openings, then the device density and integration are improved, but the integrity and uniformity of conductive layer deposition deteriorate
Solution Approach 1:
The patent changes the deposition parameters by using atomic layer deposition (ALD) with specific control over deposition temperature, pressure, and precursor flow rates. This enables precise control of film thickness and composition, achieving uniform conductive layers in high aspect ratio openings while maintaining high device density
Solution Approach 2:
The patent replaces conventional physical vapor deposition or chemical vapor deposition methods with atomic layer deposition (ALD). ALD provides superior conformal coverage and thickness control through its sequential, self-limiting surface reactions, ensuring uniform conductive layer formation in complex three-dimensional structures
2Reliability
If conductive layers are deposited in high aspect ratio openings, then the transistor performance is improved, but deposition defects and non-uniformity increase
Solution Approach 1:
The patent introduces an intermediary layer between the substrate and the conductive layer to facilitate uniform deposition. This intermediate layer provides a controlled surface that promotes consistent nucleation and growth of the conductive material, reducing deposition defects while maintaining high transistor performance
Solution Approach 2:
The patent employs continuous atomic layer deposition cycles with optimized precursor pulsing and purging sequences. This continuous process ensures complete and uniform coverage of conductive layers in high aspect ratio openings, minimizing voids and defects while maintaining high transistor performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed method enhances the integrity and performance of semiconductor devices by ensuring uniform and conformal deposition of conductive layers, reducing defects and improving the overall manufacturing process efficiency.
Implementation Method 1
A novel process involving atomic layer deposition (ALD) is used to form conductive layers with precise control
Data Source
AI summary
In method of manufacturing a semiconductor device, an opening is formed over a first conductive layer in a dielectric layer, a second conductive layer is formed over the first conductive layer in the opening without forming the second conductive layer on at least an upper surface of the dielectric layer, a third conductive layer is formed over the second conductive layer in the opening without forming the third conductive layer on at least an upper surface of the dielectric layer, and an upper layer is formed over the third conductive layer in the opening.