Semiconductor Fabrication Using Selective Wet Etch
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Solution Overview
Problem
Semiconductor devices face etching damage and electrical issues due to insufficient etchant selectivity during the etching process, which affects the etch selectivity between layers.
Innovation Solution
A fabricating method for semiconductor devices that involves forming thin gate dielectric layers in regions with different initial voltages, using a wet etch process with high etch selectivity to remove the conductive layers and gate dielectric layers outside the active regions, thereby preventing damage to the active regions and reducing the risk of electrical issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional etching process is used, then the etching process can be completed, but etching damage occurs and electrical issues arise due to insufficient etch selectivity between layers
Solution Approach 1:
The patent segments the etching process into multiple sequential steps with different etchants. First, a thick gate dielectric layer is removed using a first etchant, then a thin gate dielectric layer is removed using a second etchant with different selectivity. This segmentation allows each etching step to have optimized selectivity for its target layer, preventing etching damage to underlying active regions while maintaining electrical performance.
Solution Approach 2:
The patent changes the chemical parameters of the etching process by using different etchants with different selectivity ratios for different layers. The first etchant is formulated with high selectivity for the thick gate dielectric layer, while the second etchant is formulated with high selectivity for the thin gate dielectric layer. This parameter change in etchant composition resolves the contradiction by enabling selective removal of each layer without damaging others.
2Productivity
If the gate dielectric layer is made thin to reduce etching time, then etching efficiency improves, but the layer becomes more susceptible to damage
Solution Approach 1:
The patent applies preliminary action by first removing the thick gate dielectric layer before removing the thin gate dielectric layer. This preliminary removal of the thicker layer reduces the overall etching burden and allows the subsequent etching of the thin layer to be performed with greater precision and control, minimizing damage risk while maintaining efficiency.
Solution Approach 2:
The patent changes the etching parameters by using a two-stage etching approach with different etchants optimized for each stage. The first etchant is designed for removing thick layers efficiently, while the second etchant is designed for precise removal of thin layers with high selectivity. This parameter optimization allows the thin gate dielectric layer to be removed quickly without compromising its integrity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces the risk of etching damage and electrical issues by using a wet etch process with high selectivity, ensuring that the active regions are protected and the etching process is completed efficiently, minimizing the likelihood of leakage current and current double hump issues.
Implementation Method 1
a wet etch process is performed to remove the first conductive layer and the first gate dielectric layer outside the first region
Data Source
AI summary
A method for fabricating a semiconductor device includes: forming a first gate dielectric layer in a first and a second regions of a peripheral region of a substrate; forming a first conductive layer and a first hard mask layer over the substrate; forming a first mask layer on the first hard mask layer in the first region; removing the first hard mask layer outside the first region; removing the first hard mask layer; performing a wet etch process by taking the first hard mask layer as a mask, and removing the first conductive layer and the first gate dielectric layer outside the first region; removing the first hard mask layer and the first conductive layer; forming a second gate dielectric layer in the second region; and forming a first and a second gate conductive layers in the first and the second regions respectively.