Self-Aligned Semiconductor Conductor via Selective Etch
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Solution Overview
Problem
Existing semiconductor manufacturing processes face challenges in achieving self-aligned gates while minimizing design limitations and complexity, particularly in forming transistors with III/V materials, where ion implantation results in poor contact quality and high temperature processing affects the gate-channel interface.
Innovation Solution
A process involving epitaxial growth of a contact layer and a support layer, where the support layer is etched at a higher rate than the contact layer, allowing for the formation of a trench and a self-aligned conductor without an etch stop layer, providing design flexibility and reducing capacitive coupling, enabling shorter gate lengths and improved contact quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If ion implantation followed by doping activation anneal is used to form source and drain regions, then self-alignment of gate to channel region is achieved, but the gate-channel interface is adversely affected by high temperature processing
Solution Approach 1:
The gate structure is formed first as a preliminary step, serving as a self-aligned mask that defines the precise location of source and drain regions before any high temperature processing occurs. This preliminary gate formation ensures accurate alignment while protecting the gate-channel interface from subsequent thermal damage during doping activation anneal.
Solution Approach 2:
A sacrificial layer is introduced as an intermediary element between the gate structure and the source/drain formation process. This sacrificial layer enables the formation of highly doped source and drain regions while protecting the gate-channel interface from direct exposure to high temperature processing, as the sacrificial layer absorbs the thermal stress.
2Manufacturing precision
If ion implantation is used for doping, then self-aligned gate formation is achieved, but contact material quality is poor in III/V materials
Solution Approach 1:
The mechanical ion implantation process is replaced with an in-situ doping method where the semiconductor layer is grown with predetermined doping concentrations directly during epitaxial growth. This substitution eliminates the harmful effects of ion implantation on III/V material contact quality while maintaining precise gate self-alignment through the sacrificial layer approach.
3Manufacturing precision
If dummy gate structure with dielectric layer deposition and CMP planarization is used, then gate-last self-aligned process is achieved, but design flexibility is limited and process complexity increases
Solution Approach 1:
The complex dielectric layer deposition and CMP planarization steps are extracted and removed from the process flow. Instead, a simplified approach using a sacrificial layer that can be selectively removed is employed, maintaining gate self-alignment while significantly reducing process complexity and design constraints.
Solution Approach 2:
The conventional gate-last approach is inverted by forming the gate structure first as a sacrificial element, then using it as a self-aligned mask for source/drain formation, and finally removing it to create the actual gate trench. This inversion simplifies the process by eliminating multiple deposition and planarization steps while maintaining precise alignment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This process enables the fabrication of semiconductor devices with reduced series resistance, improved contact quality, and design flexibility, making them suitable for high-frequency applications while maintaining simplicity and efficiency.
Implementation Method 1
epitaxially growing a contact layer in contact with the channel layer
Implementation Method 2
epitaxially growing a support layer on the contact layer
Implementation Method 3
forming a trench extending through the support layer by removing the mask
Data Source
Figure 1a
Figure 1b~1g
Figure 1h~1j
AI summary
According to one aspect of the inventive concept there is provided a process for manufacturing a semiconductor device, comprising: providing a channel layer (104), providing a mask (106) on the channel layer, epitaxially growing a contact layer (108) in contact with the channel layer, epitaxially growing a support layer (110) on the contact layer, wherein the support layer is arranged to be etched at a higher rate than the contact layer, forming a trench extending through the support layer by removing the mask, and providing a conductor (118) in the trench. There is also provided an intermediate product for the manufacture of a semiconductor device.