Self-Aligned Contacts in Semiconductor Devices via Sidewall Spacers
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Solution Overview
Problem
The existing semiconductor device manufacturing processes face challenges in forming contacts due to image distortions from Optical Proximity Effects in photolithography, leading to defects like voids and parasitic resistances, especially when forming gate and source/drain contacts, which complicates the selection of manufacturing processes and increases parasitic resistances.
Innovation Solution
A method is developed to fabricate semiconductor devices with self-aligned contacts by forming gate lines, sidewall spacers, and conductive sidewall spacers, which are then cut at predetermined positions using reactive ion etching or laser cutting, eliminating the need for traditional contact hole etching and ensuring electrical isolation between devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional contact hole etching is used to form contacts on gates and source/drain, then contacts can be formed, but image distortions from Optical Proximity Effects cause defects like voids and increase parasitic resistances
Solution Approach 1:
The patent divides the contact formation process into two separate etching steps: first forming gate contacts through the gate region, then forming source/drain contacts through the source/drain regions. This segmentation allows each etching step to be optimized independently, avoiding the image distortions and defects caused by attempting to form all contacts in a single photolithography exposure step.
2Productivity
If all contact holes are etched to their bottoms at one time, then contacts can be formed efficiently, but strict demands on etching depth control cause shorts between gate and contact hole or under-etching
Solution Approach 1:
The patent segments the contact formation into sequential steps: first etching gate contact holes to the gate bottom, then etching source/drain contact holes to the source/drain bottoms. This eliminates the need to control multiple different etching depths in a single step, as each etching process targets a specific depth requirement for its respective region.
Solution Approach 2:
The patent performs the gate contact hole etching first, establishing the gate contact structure before proceeding to source/drain contact formation. This preliminary action allows subsequent source/drain etching to be performed with different depth parameters without affecting the already-formed gate contacts.
3Manufacturing precision
If sidewall spacers are formed surrounding gates with cuts, then gate patterns are defined, but sidewall spacer material enters inside cuts causing voids and defects
Solution Approach 1:
The patent performs the cutting step to define gate patterns and create isolation regions before forming the sidewall spacers. By establishing the cut boundaries in advance, the subsequently deposited sidewall spacer material is prevented from entering the cut regions, eliminating the source of voids and defects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the formation of contacts, eliminates defects like voids, and achieves good electrical isolation between devices, reducing parasitic resistances and improving the overall quality of semiconductor devices by forming contacts as sidewall spacers that are self-aligned to source/drain regions.
Implementation Method 1
cutting off the gate lines, the gate sidewall spacers and the conductive sidewall spacers at predetermined positions
Implementation Method 2
cutting off the gate lines, the gate sidewall spacers and the conductive sidewall spacers at predetermined positions
Data Source
AI summary
A semiconductor device structure is provided. The semiconductor device includes a semiconductor substrate, a first device, and a second device. Each of the first and second devices includes a gate extending in a first direction, source/drain regions respectively formed on opposite first and second sides of the gate, dielectric spacers formed respectively on outer sidewalls of the gate on the first side and the second side, and conductive spacers serving contacts to the source/drain regions and formed respectively on outer sidewalls of the respective gate spacers. A second direction from the source/drain region on the first side to the source/drain region on the second side crosses the first direction.