Self-Aligned Conductive Connecting Portions in Semiconductor Structures

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Solution Overview

Problem

As semiconductor devices miniaturize, accurately positioning electrical connecting pads becomes increasingly difficult, affecting conductive performance if incorrectly placed.

Innovation Solution

A semiconductor structure with through vias and self-aligned deposition processes to form conductive connecting portions, ensuring precise placement and improved conductivity, using copper and copper-germanium alloy materials with protection layers to enhance manufacturing efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If semiconductor devices are miniaturized to reduce size, then device size is reduced, but positioning precision of electrical connecting pads deteriorates

Engineering Contradiction:
Improvedevice sizeVSAvoidpositioning precision of electrical connecting pads
Core Design Contradiction:
Volume of moving objectVSManufacturing precision

Solution Approach 1:

The patent applies preliminary action by forming the upper conductive connecting portion before finalizing the positions of through semiconductor vias. The self-aligned deposition process pre-establishes the conductive connecting structure, which then automatically aligns with the via positions, eliminating the need for precise manual positioning of electrical connecting pads in miniaturized devices.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements self-service through self-aligned deposition where the upper conductive connecting portion automatically positions itself relative to the through semiconductor vias. The deposition process uses the vias themselves as alignment references, allowing the structure to self-correct and self-position without external intervention, thereby maintaining high positioning precision even as device size reduces.

Inventive Principle:
Principle #25Self-service

2Device complexity

If conventional deposition processes are used for forming conductive connecting portions, then process simplicity is maintained, but positioning accuracy of conductive connecting portions deteriorates

Engineering Contradiction:
Improveprocess simplicityVSAvoidpositioning accuracy of conductive connecting portions
Core Design Contradiction:
Device complexityVSManufacturing precision

Solution Approach 1:

The self-aligned deposition process allows the upper conductive connecting portion to automatically align with the through semiconductor vias during deposition. The via structures serve as self-references that guide the deposition process, enabling the system to self-position the conductive material without requiring complex external alignment mechanisms or multiple lithography steps.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent uses the through semiconductor vias as an intermediary element that mediates between the deposition process and the final positioning of the upper conductive connecting portion. The vias act as a physical template or mediator that transfers the positional information from the substrate level to the upper conductive layer, ensuring accurate alignment without direct intervention.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The design allows for precise placement of conductive connecting portions, thereby enhancing the conductive performance and reliability of semiconductor devices.

Implementation Method 1

forming an upper conductive connecting portion laterally connected to a first upper lateral surface of the first upper end and a second upper lateral surface of the second upper end by a self-aligned deposition process

Methodology Applied
Scientific EffectSelf-aligned deposition: Deposition (physical)

Data Source

PatentUS11721610B2Method for manufacturing semiconductor structure same
Publication Date: 2023.08.08 NAN YA TECH
  • US11721610B2 patent drawing
  • US11721610B2 patent drawing
  • US11721610B2 patent drawing

AI summary

The present disclosure provides a method for manufacturing a semiconductor structure. The method includes providing an underlying semiconductor layer; depositing an insulation layer over the underlying semiconductor layer; forming a first through semiconductor via extending continuously through the insulation layer; forming a second through semiconductor via extending continuously through the insulation layer; etching a portion of the insulation layer to expose a first upper end of the first through semiconductor via above the insulation layer and a second upper end of the second through semiconductor via above the insulation layer; and forming an upper conductive connecting portion laterally connected to a first upper lateral surface of the first upper end and a second upper lateral surface of the second upper end by a self-aligned deposition process.