Semiconductor Doping Structure With Self-Aligned Hard Mask Implantation

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Solution Overview

Problem

Existing semiconductor manufacturing methods face challenges in accurately aligning doping regions, leading to misalignment errors and suboptimal performance in high-pressure, high-temperature, and high-frequency applications.

Innovation Solution

The use of patterned hard masks in a self-aligned manner to form doping regions through sequential implantation processes, ensuring precise positioning and reducing misalignment errors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional doping alignment methods are used, then manufacturing process is simpler, but alignment precision deteriorates leading to misalignment errors

Engineering Contradiction:
Improvedoping region alignment precisionVSAvoidmanufacturing process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by forming the first patterned hard mask before the implantation processes. This pre-formed mask serves as a reference structure that enables self-aligned doping, where subsequent doping regions are positioned relative to this initial mask pattern, ensuring precise alignment without requiring complex real-time alignment procedures during implantation.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements self-service through self-aligned doping where the previously formed doped regions and their associated hard masks automatically serve as alignment references for subsequent doping steps. The process uses the existing structures on the wafer to define the positions of new doped regions, eliminating the need for external alignment systems and reducing misalignment errors.

Inventive Principle:
Principle #25Self-service

2Manufacturing precision

If multiple separate alignment processes are used, then alignment precision may improve, but manufacturing time increases

Engineering Contradiction:
Improvedoping region alignment precisionVSAvoidmanufacturing cycle time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The patent merges multiple alignment operations into a single self-aligned doping sequence. By using the first patterned hard mask and subsequently formed doped regions as integrated alignment references, the method combines what would otherwise be separate alignment and doping steps into a unified process flow, reducing the total number of alignment operations and manufacturing cycle time.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The preliminary formation of the first patterned hard mask establishes an alignment reference that eliminates the need for subsequent alignment operations. This pre-established reference structure allows all subsequent doping regions to be positioned automatically relative to it, consolidating multiple alignment steps into one preliminary action that speeds up the overall manufacturing process.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method enables accurate doping positioning, enhancing the performance of semiconductor structures for high-power and high-frequency applications by minimizing alignment errors and improving electrical characteristics.

Implementation Method 1

performing a first implantation process using the first patterned hard mask to form a first doped region in the epitaxial layer; performing a second implantation process using the first patterned hard mask to form a second doped region in the epitaxial layer

Methodology Applied
Scientific EffectIon Implantation: Ion Implantation

Data Source

PatentUS20250210353A1Semiconductor Structures and Manufacturing Methods Thereof
Publication Date: 2025.06.26 DIODES INC
  • US20250210353A1 patent drawing
  • US20250210353A1 patent drawing
  • US20250210353A1 patent drawing

AI summary

A semiconductor structure manufacturing method includes forming, on a protective layer that is disposed on an epitaxial layer, a first patterned hard mask including an opening surrounded by side surfaces of the first patterned hard mask and exposing a first portion of the protective layer. A first doped region is formed in a portion of the epitaxial layer below the opening through the first patterned hard mask. A second patterned hard mask is formed on the side surfaces of the first patterned hard mask, through which a second doped region is formed in the first doped region. The second patterned hard mask and a portion of the first patterned hard mask are removed, and a remaining portion of the first patterned hard mask forms a third patterned hard mask, through which a second portion of the protective layer is removed.