Semiconductor Self-Aligned Patterning for Sub-20 nm Features
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current methods for generating sub 20 nm features in semiconductor patterning, such as EUV lithography and maskless electron beam lithography, face challenges like high costs, low throughput, and material limitations due to chemical reactions and processing temperatures.
Innovation Solution
A semiconductor self-aligned patterning method involving a substrate with multiple layers, where a first pattern is formed, followed by conformal layer deposition and selective etching to create a second pattern with minimal feature sizes below 20 nm, utilizing different materials for each layer and achieving high etching selectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If EUV lithography is used to generate sub 20 nm features, then minimal feature size is reduced, but cost increases and throughput decreases
Solution Approach 1:
The patent divides the patterning process into multiple sequential steps: forming mandrels at a first pitch, depositing spacers to create patterns at a second (smaller) pitch, then repeating the process with additional mandrels and spacers. This multi-stage segmentation enables achievement of sub-20nm features through conventional lithography that would otherwise require EUV, while maintaining higher throughput by avoiding EUV's single-step limitations.
2Manufacturing precision
If chemical reactions are used for pattern formation, then sub 20 nm features are formed, but material selection is limited and processing temperature is constrained
Solution Approach 1:
The patent replaces chemical reaction-based patterning with a physical deposition and etching process. Instead of relying on chemical cross-linking between resist layers, the method uses conformal physical vapor deposition to deposit spacer materials uniformly around mandrels, followed by anisotropic etching to transfer the pattern. This mechanical/physical substitution eliminates chemical reaction constraints, enabling broader material selection and higher processing temperature compatibility.
3Manufacturing precision
If conformal layer deposition and selective etching are used, then etching selectivity is improved, but process complexity increases
Solution Approach 1:
The patent applies preliminary conformal deposition of spacer materials around mandrels before the actual pattern transfer etching. This preliminary action creates a protective spacer layer that defines the final pattern dimensions with high precision. The spacer layer acts as a self-aligned mask, eliminating the need for separate alignment steps and providing inherent etching selectivity through the spacer's material properties, thereby simplifying the overall process despite the additional deposition step.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the production of semiconductor chips with feature sizes as small as 7-10 nm without relying on EUV or chemical reactions, overcoming material and temperature limitations, and achieving high etching selectivity for precise patterning.
Implementation Method 1
thinning the first conformal layer and the second conformal layer alternatively to form a second pattern
Data Source
AI summary
A method for semiconductor self-aligned patterning includes steps of providing a substrate comprising a first layer and a second layer, wherein the first layer is on top of the second layer; removing a portion of the first layer to form a first pattern; depositing a first conformal layer on the first pattern; depositing a second conformal layer on the first conformal layer; removing a portion of the second conformal layer to expose a portion of the first conformal layer; and thinning the first conformal layer and the second conformal layer alternatively to form a second pattern. A semiconductor self-aligned structure is also provided.