Self-Aligned Sidewall Spacers for Semiconductor Packing Density
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Solution Overview
Problem
Conventional semiconductor device fabrication techniques face limitations in reducing device size without pushing the expensive lithography process further, hindering the increase in device-packing density and IC complexity.
Innovation Solution
A self-aligned device structure method is developed, involving a semiconductor substrate with an active area surrounded by an isolation structure, sequential layer formation, patterning, and the use of composite spacers to form a self-aligned structure, allowing for reduced device dimensions without relying on advanced lithography.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional lithography processes are used, then manufacturing cost is controlled, but device size cannot be reduced further
Solution Approach 1:
The patent transitions from planar 2D device layout to 3D vertical structures by forming sidewall spacers and stacked layers. The active area width W is reduced from approximately 6Rm to 3Rm by utilizing vertical spacer structures that define contact regions without requiring additional lateral lithographic resolution
Solution Approach 2:
The sidewall spacers are formed through self-aligned processes where the spacer material automatically deposits on the sidewalls of previously formed structures. This self-alignment eliminates the need for additional lithographic steps to define contact regions, enabling smaller device dimensions using existing lithography capabilities
2Productivity
If device size is reduced to increase packing density, then productivity increases, but manufacturing precision requirements worsen
Solution Approach 1:
The self-aligned sidewall spacer formation process automatically defines contact region positions based on gate structure geometry, eliminating alignment errors that would accumulate through multiple lithographic steps. This self-definition mechanism maintains manufacturing precision while enabling reduced feature sizes
Solution Approach 2:
The patent changes the controlling parameter for device dimensions from lithographic resolution Rm to spacer thickness, which can be precisely controlled through deposition processes. This parameter transformation allows device dimensions to be scaled independently of lithography limits, maintaining precision while reducing size
Data Source
AI summary
A method for fabricating a semiconductor integrated circuit having a self-aligned structure, the method comprises the steps of: providing a semiconductor substrate; forming a gate dielectric layer, a first polysilicon layer, and a first capping layer on top of the semiconductor substrate; patterning the first capping layer, the first polysilicon layer and stopping on the gate dielectric layer to form a gate structure; forming and patterning a composite dielectric layer, a second polysilicon layer, and a second capping layer to form an interconnect structure; forming a composite spacer; removing the photo-resist layer; forming a third polysilicon layer; making blanket removal of the third polysilicon layer to leave a remain third polysilicon layer; removing the first and the second capping layer; forming a source and a drain; and forming a silicide layer overlying the gate structure, source, drain and the interconnect structure to form the self-aligned structure.