Self-Aligned Variable Resistance Pattern in Cross-Point Semiconductor Devices
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Solution Overview
Problem
In the manufacturing of semiconductor devices with cross-point array structures, achieving precise alignment between lower and upper patterns is challenging, leading to mis-alignment issues that affect the electrical characteristics and reliability of the devices.
Innovation Solution
The semiconductor device design includes a substrate with first and second insulation patterns that extend between conductive lines and structures, forming openings where a variable resistance pattern and electrode are self-aligned, reducing mis-alignment through specific etching processes and spacer formations, allowing for precise alignment and improved electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional manufacturing processes are used for cross-point array structures, then manufacturing simplicity is maintained, but alignment precision between lower and upper patterns deteriorates
Solution Approach 1:
The patent applies preliminary action by forming insulation patterns and spacers before the final variable resistance pattern formation. The insulation patterns are deposited and etched to create predefined regions that guide subsequent pattern formation, ensuring alignment is established early in the process before critical dimensions are finalized.
Solution Approach 2:
The patent uses insulation patterns as intermediary structures that mediate between the substrate and the variable resistance patterns. These insulation patterns serve as alignment references and physical guides that ensure precise positioning of upper patterns relative to lower patterns without requiring direct measurement or complex alignment systems.
Solution Approach 3:
The manufacturing process is segmented into distinct stages: forming insulation patterns, forming spacers on insulation patterns, forming variable resistance patterns, and forming electrodes. Each stage produces alignment references for the next stage, breaking down the complex alignment problem into manageable sequential steps that accumulate precision.
2Reliability
If alignment tolerance is relaxed to simplify manufacturing, then device reliability deteriorates due to mis-alignment
Solution Approach 1:
The patent implements beforehand cushioning by creating multiple alignment reference structures (insulation patterns and spacers) that provide tolerance buffering. These structures are formed with sufficient dimensional margins and interlocking geometries that accommodate manufacturing variations while maintaining functional alignment, preventing misalignment from propagating through the device.
Data Source
AI summary
A semiconductor device includes first conductive lines and first and second insulation patterns on a substrate, first structures spaced apart from each other on the first conductive lines, a variable resistance pattern on the first structures, and a second electrode on the variable resistance pattern. The first conductive lines extend in a first direction. The first structures include a switching pattern and a first electrode sequentially stacked. The first insulation pattern fills a space between the first structures in a second direction and the first insulation pattern has a first top surface higher than a top surface of the first structures. The second insulation pattern fills a space between the first structures in the first direction, and the second insulation pattern has a second top surface higher than a top surface of the first structures. The variable resistance pattern fills an opening defined by the first and second insulation patterns.