Semiconductor Self-Test Address Generation Circuit
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Solution Overview
Problem
The increasing complexity of semiconductor devices leads to longer test times and higher costs during the evaluation of their reliability, necessitating more efficient testing methods before and after packaging.
Innovation Solution
A semiconductor system comprising a first and second semiconductor device, where the second device includes a control signal generating unit, address generating units, and an operation control unit that automatically generate read/write and selection control signals, and address signals in response to an active signal, enabling sequential read and write operations of memory cells by counting up in synchronization with pulses, thereby reducing total test time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional testing methods are used for semiconductor devices, then reliability evaluation can be performed, but test time increases and costs increase
Solution Approach 1:
The patent implements self-testing functionality within the semiconductor device itself. The test signal generating unit and test result analyzing unit are integrated into the device, allowing it to automatically generate test signals, control memory operations, and analyze test results without requiring external testing equipment. This self-service approach significantly reduces test time while maintaining reliability evaluation capabilities.
Solution Approach 2:
The patent performs reliability evaluation during the manufacturing process rather than after packaging. By integrating test functionality into the semiconductor device before packaging, reliability can be assessed in advance, enabling early detection of defects and reducing the need for time-consuming post-packaging testing.
2Reliability
If traditional testing methods are used for semiconductor devices, then reliability evaluation can be performed, but testing costs increase
Solution Approach 1:
The patent implements self-testing functionality within the semiconductor device itself. The test signal generating unit and test result analyzing unit are integrated into the device, allowing it to automatically generate test signals, control memory operations, and analyze test results without requiring external testing equipment. This self-service approach significantly reduces test time while maintaining reliability evaluation capabilities.
Solution Approach 2:
The patent performs reliability evaluation during the manufacturing process rather than after packaging. By integrating test functionality into the semiconductor device before packaging, reliability can be assessed in advance, enabling early detection of defects and reducing the need for time-consuming post-packaging testing.
3Productivity
If Built-In Self-Test (BIST) circuit is added to semiconductor device, then testing efficiency improves, but device complexity increases
Solution Approach 1:
The patent integrates multiple functions into the semiconductor device: normal data storage operations and self-testing operations share the same memory array and control logic. The test signal generating unit can operate in both testing mode and normal operation mode, and the test result analyzing unit processes both test data and normal read data. This multi-functionality approach enables self-testing without proportionally increasing device complexity.
Data Source
AI summary
A semiconductor device includes a control signal generating unit, a first address generating unit, and a second address generating unit. The control signal generating unit generates a read/write control signal and a selection control signal in response to an active signal. The first address generating unit generates a first address signal in response to the selection control signal and a second address signal. The second address generating unit generates the second address signal in response to the read/write control signal and the first address signal.