Semiconductor Integrated Circuit Self-Testing Reference Core
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Solution Overview
Problem
Existing semiconductor integrated circuits face challenges in detecting failures during field tests, particularly in high-reliability applications, as traditional logic BIST methods rely on fixed parameters that may not detect all failures, leading to a decreased failure detection rate.
Innovation Solution
The semiconductor integrated circuit employs a multi-core structure with a reference core that continuously generates and updates test patterns, allowing for comparison with test-target cores to detect failures that might be missed by fixed parameters, thereby improving failure detection rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fixed parameters are used in logic BIST for field testing, then the testing process is simple and reliable, but the failure detection rate decreases because fixed parameters cannot detect all failures
Solution Approach 1:
The patent applies dynamics by transitioning from fixed test parameters to dynamic test parameters. The reference core continuously generates and updates test patterns, making the testing parameters adaptable and changing over time. This dynamic approach enables the detection of failures that fixed parameters would miss, while the system maintains self-contained operation without external parameter updates.
Solution Approach 2:
The patent implements feedback through the reference core that continuously monitors its own test results and uses this information to generate updated test patterns. The comparison between the test-target core and reference core creates a feedback loop where the system learns from its own operation and adjusts test parameters accordingly, improving failure detection capability.
2Reliability
If a reference core is added to improve failure detection, then the failure detection rate improves, but the device complexity increases
Solution Approach 1:
The reference core is designed with multi-functionality, serving both as a test target and as a reference for comparison. It performs the same functions as regular cores while additionally providing reference test patterns and results for failure detection. This universal design minimizes the increase in device complexity by making existing components serve dual purposes.
Solution Approach 2:
The patent uses copying by creating a reference core that replicates the structure and functionality of test-target cores. This copy allows for direct comparison of test results without requiring fundamentally different hardware architectures, thereby improving failure detection while limiting the increase in device complexity.
Data Source
AI summary
According to one embodiment, a semiconductor integrated circuit includes: a first core that includes a first logic circuit that has a plurality of first scan chains, and a first generator that generates a first test pattern; a second core that includes a second logic circuit that has a plurality of second scan chains, and a second generator that generates a second test pattern; a controller that controls a test operation of the first and second cores. The controller is configured to: obtain a seed for a test pattern from the first generator; supply the obtained seed to the second generator; perform a test on the first and second cores for a same number of cycles; obtain first and second test results respectively from the first and second cores; and compare the first and second test results.