Semiconductor Device Semi-Insulating Interface Layer RF Loss Reduction
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Solution Overview
Problem
High-resistivity silicon substrates used in RF circuits face issues with parasitic surface channels that increase substrate loss and variability, leading to reduced effective resistivity and high-frequency power losses.
Innovation Solution
A semi-insulating material is deposited at the interface between the semiconductor substrate and dielectric layer, forming an electroconductive channel within the semi-insulating region rather than the substrate, using materials like SiC or SIPOS, which have high resistivity and low temperature dependence, thereby minimizing effective substrate resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If a high-resistivity silicon substrate is used to achieve high-quality passive components and excellent thermal conductivity, then the thermal management and passive component performance are improved, but parasitic surface channels form at the silicon/silicon-dioxide interface causing increased substrate loss and excessive variation of effective substrate resistivity
Solution Approach 1:
A semi-insulating layer is introduced as an intermediary between the high-resistivity silicon substrate and the silicon dioxide layer. This intermediate layer prevents direct contact between the substrate and oxide, thereby eliminating the formation of parasitic surface channels at the interface while preserving the excellent thermal conductivity of the silicon substrate and maintaining high-quality passive components
2Loss of energy
If a polycrystalline or amorphous silicon region is formed by ion implantation to counteract high-frequency power losses, then the conductivity of inversion or accumulation channels is limited, but thermal treatment at high temperature restores the crystallinity and reduces charge trap concentration, allowing electroconductive channel formation
Solution Approach 1:
The semi-insulating layer serves as a stable intermediary that maintains its high-resistivity properties throughout the manufacturing process, including thermal treatments. Unlike polycrystalline or amorphous silicon regions that lose their effectiveness after thermal processing, the semi-insulating layer consistently prevents electroconductive channel formation, ensuring reliable substrate resistivity
Solution Approach 2:
The invention changes the material parameter of the interface layer from polycrystalline/amorphous silicon to semi-insulating material with superior thermal stability. This parameter change ensures that the layer maintains its high-resistivity characteristics even after exposure to high temperatures during semiconductor manufacturing, preventing channel formation under various processing conditions
3Ease of manufacture
If ion implantation is used to form a damaged crystal structure region with charge traps, then the manufacturing process is established, but the region shows reduced effectiveness when thermal treatment restores crystallinity
Solution Approach 1:
The semi-insulating layer acts as a robust intermediary that maintains its functionality throughout the manufacturing process. Unlike ion-implanted regions that require precise damage control, the semi-insulating layer naturally maintains high resistivity through its material properties, providing reliable channel conductivity control without being sensitive to manufacturing variations
Solution Approach 2:
The semi-insulating layer can be formed through deposition processes that are simpler and more reliable than ion implantation. The layer serves its purpose effectively without requiring subsequent thermal annealing or complex process steps to maintain its properties, making the manufacturing process more robust and easier to control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces substrate losses and variability, maintaining high resistivity while enabling efficient high-frequency performance by forming the electroconductive channel in a semi-insulating region, thus optimizing the semiconductor device's conductivity and stability.
Implementation Method 1
the region is formed by means of deposition and comprises a semi-insulating material
Data Source
AI summary
The invention relates to a semiconductor device (10) comprising a semiconductor body (1) with a high-ohmic semi-conductor substrate (2) which is covered with a dielectric layer (3, 4) containing charges, on which dielectric layer one or more passive electronic components (20) comprising conductor tracks (20) are provided, wherein, at the location of the passive elements (20), a region (5) is present at the interface between the semiconductor substrate (2) and the dielectric layer (3, 4), as a result of which the conductivity of an electrically conducting channel induced in the device (10) by the charges is limited at the location of the region (5). According to the invention, the region (5) is formed by deposition and comprises a semi-insulating material. As a result, the device (10) has a very low high-frequency power loss because the inversion channel is formed in the semi-insulating region (5). The device (10) further allows for a higher temperature budget and hence for the integration of active semiconductor elements (8) into the semiconductor body (1). A very suitable semi-insulating material for the region (5) is SiC, SIPOS or POLYDOX.