Semiconductor Device Carrier Clearance for Sense Current Detection

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Solution Overview

Problem

The existing semiconductor device faces challenges in accurately detecting currents through sense IGBT and sense diode regions due to current interference, which affects the detection accuracy.

Innovation Solution

The semiconductor device is designed with specific structural configurations, including smaller areas for sense IGBT and sense diode regions, strategically placed n-type regions, and clearance distances that suppress carrier movement between regions, preventing current interference. This includes an n-type region across the sense IGBT and sense diode regions, and an insulating layer or high-density n-type regions between the IGBT and diode drift regions to prevent carrier flow.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If sense IGBT and sense diode are provided in the same semiconductor substrate, then current detection capability is improved, but current interference between regions occurs reducing detection accuracy

Engineering Contradiction:
Improvecurrent detection capabilityVSAvoiddetection accuracy
Core Design Contradiction:
Adaptability or versatilityVSMeasurement precision

Solution Approach 1:

The semiconductor substrate is divided into distinct main regions and sense regions, with further segmentation into IGBT and diode regions. This spatial segmentation allows independent detection of different current types while maintaining physical separation to prevent interference between sense elements.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions are assigned specific doping characteristics (n-type or p-type) and structural properties tailored to their function. The sense regions have optimized local properties including controlled clearance distances and doping concentrations that differ from main regions, enabling accurate current detection without interference.

Inventive Principle:
Principle #3Local quality

2Area of stationary object

If clearance between regions is reduced, then device area is reduced, but carrier movement between regions increases causing current interference

Engineering Contradiction:
Improvedevice areaVSAvoidcurrent interference
Core Design Contradiction:
Area of stationary objectVSObject-generated harmful factors

Solution Approach 1:

The clearance distances between regions are precisely controlled to exceed specific thresholds determined by carrier mobility and lifetime parameters. This parameter optimization ensures that while the device area is minimized, the clearance is sufficient to suppress carrier diffusion and drift between adjacent regions, preventing current interference.

Inventive Principle:
Principle #35Parameter changes

3Ease of manufacture

If n-type region is provided across sense regions, then structural integration is improved, but carrier diffusion between IGBT and diode regions may occur

Engineering Contradiction:
Improvestructural integrationVSAvoidcarrier diffusion
Core Design Contradiction:
Ease of manufactureVSObject-generated harmful factors

Solution Approach 1:

The n-type region is provided with locally optimized properties including specific doping concentrations and clearance distances to adjacent regions. These local quality adjustments ensure that while the n-type region provides structural integration across sense regions, carrier diffusion between IGBT and diode regions is suppressed through controlled geometric and electrical parameters.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively suppresses current interference between the sense IGBT and sense diode regions, allowing for accurate detection of currents in each region, aligning the current ratios with their respective area ratios, thus enhancing detection accuracy.

Implementation Method 1

the clearance between the body region and the anode region is longer than a product of electron mobility and electron lifetime in the n-type region between the body region and the anode region. Accordingly, movement of carriers between the body region and the anode region is suppressed.

Methodology Applied
Scientific EffectCarrier movement suppression through clearance design:

Implementation Method 2

the clearance between the anode region and the collector region is longer than a product of electron mobility and electron lifetime in the n-type region between the anode region and the collector region. Accordingly, movement of carriers between the anode region and the collector region is suppressed.

Methodology Applied
Scientific EffectCarrier movement suppression through clearance design:

Implementation Method 3

the clearance between an end of the collector region on a sense diode region side and the body region is longer than a product of electron mobility and electron lifetime in the n-type region between the end and the body region. the movement of carriers between the cathode and the body region is suppressed.

Methodology Applied
Scientific EffectCarrier movement suppression through clearance design:

Data Source

PatentUS9972707B2Semiconductor device
Publication Date: 2018.05.15 DENSO CORP
  • US9972707B2 patent drawing
  • US9972707B2 patent drawing
  • US9972707B2 patent drawing

AI summary

A semiconductor device includes a main IGBT region in which an IGBT is provided, a main diode region in which a diode is provided, a sense IGBT region in which an IGBT is provided, and a sense diode region in which a diode is provided. A clearance between the body region and the anode region is longer than a product of electron mobility and electron lifetime in the n-type region between the body region and the anode region. A clearance between an end of the collector region on a sense diode region side and the body region is longer than a product of electron mobility and electron lifetime in the n-type region between the end and the body region.