Semiconductor Shallow Wells Prevent Gate Dielectric Breakdown
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Solution Overview
Problem
Semiconductor devices with a triple well structure face dielectric breakdown issues in the gate insulating film due to charging during the dry etching process, leading to reliability and manufacturing yield concerns.
Innovation Solution
The implementation of a semiconductor device design that includes additional shallow wells and diffusion layers, with specific wiring and interconnection methods to discharge accumulated charge and reduce potential differences between deep and shallow wells, preventing dielectric breakdown by forming discharge paths that allow charge to be dissipated to the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a triple well structure is used to reduce power consumption during standby, then power consumption is reduced, but dielectric breakdown occurs in the gate insulating film due to charging during dry etching
Solution Approach 1:
An n-type diffusion layer is introduced as an intermediary charge discharge path between the deep n-well and the p-type substrate. This diffusion layer acts as a mediator to safely dissipate accumulated charges during dry etching, preventing dielectric breakdown while maintaining the triple well structure's power-saving benefits
Solution Approach 2:
The n-type diffusion layer is formed in advance during the well formation process, before the dry etching process occurs. This preliminary charge discharge path is prepared beforehand to prevent charge accumulation and subsequent dielectric breakdown during the etching process
2Reliability
If additional shallow wells and diffusion layers are added to prevent dielectric breakdown, then reliability is improved, but device complexity increases
Solution Approach 1:
The n-type diffusion layer is merged with the existing deep n-well structure, forming an integrated charge discharge path. The diffusion layer shares the same conductivity type and functional purpose as the deep n-well, allowing it to be incorporated into the existing triple well architecture without creating entirely separate structures
Solution Approach 2:
The n-type diffusion layer serves multiple functions: it acts as a charge discharge path during dry etching, provides electrical coupling between the deep n-well and substrate, and maintains potential equilibrium. This multi-functionality reduces the need for additional separate components
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents dielectric breakdown in the gate insulating film, enhancing manufacturing yield and product reliability by reducing voltage applied to the gate insulating film and eliminating potential differences between deep and shallow wells.
Implementation Method 1
forms an n-type diffusion layer in the deep n-type well to discharge charge accumulated in the deep n-type well
Implementation Method 2
during the etching of an interconnection layer by etching
Data Source
AI summary
There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer.