Semiconductor die shared bump routing layer

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Solution Overview

Problem

Conventional flip chip technology requires a large array of solder bumps on semiconductor dies, leading to increased manufacturing costs due to the difficulty in routing connections between pads and bumps, necessitating multiple routing layers.

Innovation Solution

Implementing a semiconductor die with a reduced bump-to-pad ratio by using shared bumps interconnected to multiple pads via a single pad-to-bump routing layer, thereby reducing the total number of bumps on the active surface without decreasing the number of pads that require bumps.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a large array of bumps is used to connect each pad to its corresponding bump, then the number of electrical connections is sufficient, but the routing complexity increases and manufacturing cost increases

Engineering Contradiction:

Improveelectrical connection completenessVSAvoidrouting layer complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

Multiple pads are merged to share a single bump connection. The patent implements this by configuring a routing layer where multiple pad regions converge to a common bump, reducing the total number of bumps required while maintaining all necessary electrical connections. This merging approach directly reduces routing complexity and manufacturing cost.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

Each bump is designed to serve multiple functions by connecting to multiple pads. The routing layer configuration enables a single bump to act as a universal connection point for several pads, thereby reducing the overall bump count while ensuring complete electrical connectivity across the semiconductor die.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Ease of operation

If multiple routing layers are used to connect pads and bumps, then routing flexibility is improved, but manufacturing cost increases

Engineering Contradiction:

Improverouting flexibilityVSAvoidmanufacturing cost

Core Design Contradiction:

Ease of operationVSEase of manufacture

Solution Approach 1:

The patent employs a three-dimensional routing layer structure that provides routing flexibility without requiring multiple stacked layers. By utilizing vertical vias and lateral routing paths within a single routing layer, the design achieves the flexibility of multiple layers while maintaining the manufacturing simplicity of a single layer, thereby reducing production costs.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS7663235B2Semiconductor die with reduced bump-to-pad ratio

Publication Date: 2010.02.16 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD

AI summary

According to one exemplary embodiment, a semiconductor die includes at least one pad ring situated on an active surface of the semiconductor die, where the at least one pad ring includes a number of pads. The semiconductor die further includes a number of bumps including at least one shared bump. The at least one shared bump is shared by at least two pads, thereby causing the number of bumps to be fewer than the number of pads. The at least two pads can be at least two ground pads, at least two power pads, or at least two reference voltage pads.