Semiconductor Shared Contact Plug Formation via Source-Drain Segmentation
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Solution Overview
Problem
The challenge in semiconductor manufacturing is the difficulty in forming shared contact plugs due to the high complexity and risk associated with the etching process, which can lead to mis-etching and short-circuiting issues, affecting the performance and reliability of the semiconductor structure.
Innovation Solution
The method involves forming a semiconductor structure with a shared contact region where the source/drain doped regions are differentiated into first and second regions, with specific interconnection layers and cap layers, allowing for the formation of a shared contact plug that bypasses the need to etch the source/drain cap layer, thereby simplifying the etching process and reducing the risk of mis-etching and short-circuiting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a conventional etching process is used to form shared contact plugs, then the contact plug can be formed, but the process complexity increases and the risk of mis-etching and short-circuiting increases
Solution Approach 1:
The source/drain doped regions are segmented into first source/drain doped regions (in shared contact regions) and second source/drain doped regions (not in shared contact regions). This segmentation allows different interconnection layer configurations for different regions, simplifying the etching process for shared contact plugs by avoiding the need to etch through the source/drain cap layer.
Solution Approach 2:
Different interconnection layer structures are implemented in different regions: in shared contact regions, only the second source-drain interconnection layer is formed without the source/drain cap layer, while in other regions, both layers are formed. This local differentiation simplifies the etching process specifically where needed without affecting other areas.
2Productivity
If the etching process is simplified, then the formation time is reduced, but the cross-sectional shape and opening size accuracy may be compromised
Solution Approach 1:
The source/drain cap layer is selectively omitted in shared contact regions before the etching process begins. This preliminary action ensures that when etching is performed, the etch path is already optimized, allowing faster etching without compromising the cross-sectional shape or opening size accuracy of the shared contact plugs.
3Reliability
If the source/drain cap layer is etched, then the shared contact plug can be formed, but the probability of mis-etching and short-circuiting increases
Solution Approach 1:
The source/drain cap layer is extracted (removed) from shared contact regions specifically, so it does not need to be etched during the shared contact plug formation process. This extraction eliminates the source of potential mis-etching and short-circuiting issues while maintaining the cap layer in other regions where it is needed for protection.
Data Source
AI summary
A semiconductor structure and a forming method thereof are provided. The method includes: providing a base having a gate structure, where there is a gate cap layer on the top of the gate structure, there is a source/drain doped region in the base on two sides of the gate structure, there is a bottom dielectric layer on the base, the base includes a shared contact region that is used for forming a shared contact plug, the source/drain doped region located in the shared contact region is used as a first source/drain doped region, and the remaining is used as a second source/drain doped region; forming, in a bottom dielectric layer, a first source-drain interconnection layer connected to the second source/drain doped region, and a source/drain cap layer located on the top of the first source-drain interconnection layer; forming, in the bottom dielectric layer, a second source-drain interconnection layer connected to the first source/drain doped region; forming a top dielectric layer covering the gate cap layer, the source/drain cap layer, the second source-drain interconnection layer, and the bottom dielectric layer; and forming, in the shared contact region, a shared contact plug running through the top dielectric layer and the gate cap layer. According to the present disclosure, difficulty in forming the shared contact plug is reduced, and the performance of the semiconductor structure is improved.