Semiconductor Device Shared Drain Contact Reduces Frame Area
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing display devices with liquid crystal or organic electroluminescent elements face challenges in minimizing the frame area around the display area, as peripheral circuits like CMOS circuits occupy significant space, limiting the reduction of the overall device size.
Innovation Solution
The design incorporates a semiconductor device with a semiconductor layer comprising p-type and n-type transistors, where the first drain area is in contact with the second drain area through a hole in the insulating layer, allowing for a reduced size inverter structure that minimizes the contact area with the output electrode, thereby reducing the frame area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the size of semiconductor elements such as CMOS circuits is reduced, then the frame area is reduced, but the manufacturing precision and reliability become more difficult to maintain
Solution Approach 1:
The patent merges the p-type transistor and n-type transistor into a single semiconductor layer, sharing common regions (source/drain areas) and insulating layers. This integration reduces the overall area while maintaining proper electrical isolation and functionality, thereby reducing frame area without sacrificing manufacturing precision
Solution Approach 2:
The shared insulating layer serves multiple functions: electrical isolation for both p-type and n-type transistors, structural support, and dielectric material for capacitive coupling. This multi-functionality reduces the total number of layers needed, enabling smaller device size while maintaining manufacturing feasibility
2Area of stationary object
If the size of semiconductor elements such as CMOS circuits is reduced, then the frame area is reduced, but the device complexity increases
Solution Approach 1:
The patent combines p-type and n-type transistors into a unified structure within a single semiconductor layer, sharing common source/drain areas and insulating layers. This merging approach reduces device complexity by eliminating redundant structures while achieving compact integration for smaller frame area
Solution Approach 2:
The semiconductor layer is segmented into distinct p-type and n-type regions with clearly defined channel areas, source/drain areas, and gate electrode positions. This segmentation allows independent optimization of each transistor type while maintaining overall structural simplicity and reducing manufacturing complexity
Data Source
AI summary
According to one embodiment, a semiconductor device includes first and second gate electrodes, a semiconductor layer, an output electrode, and an insulating layer. The semiconductor layer includes first source and drain areas, a first channel area facing the first gate electrode, second source and drain areas, and a second channel area facing the second gate electrode. The output electrode outputs voltage produced in the first and second drain areas. In the semiconductor device, the first drain area is in contact with the second drain area. The insulating layer includes a hole portion communicating with one of the first and second drain areas. The output electrode is in contact with one of the first and second drain areas via the hole portion.