Semiconductor Shared Gate Connection Parasitic Capacitance Reduction
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Solution Overview
Problem
Parasitic capacitance in semiconductor devices limits the operating frequency and bandwidth, particularly in high-frequency circuits, as existing technologies fail to effectively minimize unwanted capacitance between device components.
Innovation Solution
A method is introduced to fabricate semiconductor devices by forming shared source/drain connections at one planar level and shared gate connections at a different planar level, utilizing dielectric material separation to reduce parasitic capacitance between these connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If shared source/drain connections and shared gate connections are formed at the same planar level, then device complexity is reduced, but parasitic capacitance increases limiting operating frequency
Solution Approach 1:
The patent applies dimensionality change by forming the shared gate connection at a different planar level (elevated or recessed) relative to the shared source/drain connection. This vertical separation in the Z-dimension reduces parasitic capacitance between the gate and source/drain connections while maintaining the shared connection topology, thus resolving the contradiction between device complexity and parasitic capacitance.
2Area of stationary object
If device components are placed in close proximity, then area is reduced, but parasitic capacitance increases limiting bandwidth
Solution Approach 1:
The patent utilizes vertical dimensionality to separate the shared gate connection from the shared source/drain connection by forming them at different planar levels. This allows horizontal proximity for area efficiency while achieving vertical separation to minimize parasitic capacitance, effectively resolving the area versus parasitic capacitance contradiction.
Data Source
AI summary
A method for fabricating a semiconductor device includes forming a shared source/drain connection at a first planar level to connect a first source/drain contact structure disposed on a first source/drain region to a second source/drain contact structure disposed on a second source/drain region, and forming a shared gate connection to connect a first gate structure to a second gate structure. The shared gate connection is formed at a second planar level different from the first planar level to reduce parasitic capacitance between the shared source/drain connection and the shared gate connection.