Semiconductor Device with Shared Memory and Switching Circuits

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Solution Overview

Problem

The challenge is to improve arithmetic processing speed and reduce power consumption in semiconductor devices, particularly in AI technology applications where high heat generation and power consumption are issues due to increased arithmetic operations, and existing architectures like Binary Neural Networks and Ternary Neural Networks face limitations in circuit integration and wiring efficiency.

Innovation Solution

A semiconductor device with a novel structure comprising multiple arithmetic blocks and memory circuits stacked in different layers, utilizing oxide semiconductor transistors for memory and silicon transistors for arithmetic circuits, with switching circuits to efficiently transfer weight data between them, allowing for parallel processing and reduced power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple arithmetic circuits share the same weight data through separate memory-arithmetic circuit paths, then arithmetic processing capability is improved, but the number of wiring paths increases leading to higher power consumption and reduced charging/discharging speed

Engineering Contradiction:

Improvearithmetic processing speedVSAvoidpower consumption

Core Design Contradiction:

ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent merges multiple weight data storage functions into a single shared memory circuit. Instead of having separate memory circuits for each arithmetic circuit, one memory circuit serves multiple arithmetic circuits through time-multiplexed weight data supply. This reduces the total number of wiring paths between memory and arithmetic circuits, thereby reducing charge/discharge energy and power consumption while maintaining the capability to support multiple arithmetic operations.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent introduces dynamic switching mechanisms (switching circuits) that dynamically allocate weight data from the shared memory to different arithmetic circuits based on operational requirements. The system dynamically changes the connection topology and data flow paths during operation, allowing the same physical infrastructure to serve multiple functions at different time intervals, thus optimizing both performance and power efficiency.

Inventive Principle:

Principle #15Dynamics

2Productivity

If multiple arithmetic circuits share the same weight data through separate memory-arithmetic circuit paths, then arithmetic processing capability is improved, but wiring charging/discharging speed decreases

Engineering Contradiction:

Improvearithmetic processing speedVSAvoidwiring charging/discharging speed

Core Design Contradiction:

ProductivityVSSpeed

Solution Approach 1:

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

Inventive Principle:

Principle #15Dynamics

3Loss of energy

If arithmetic circuits and memory circuits are alternately arranged to shorten bit lines, then charge and discharge energy is reduced, but the area of peripheral circuits increases greatly

Engineering Contradiction:

Improvecharge and discharge energyVSAvoidarea of peripheral circuits

Core Design Contradiction:

Loss of energyVSArea of stationary object

Solution Approach 1:

Inventive Principle:

Principle #5Merging (Combining)

4Loss of energy

If a single memory circuit serves multiple arithmetic circuits through time-multiplexed weight data supply, then power consumption and area are reduced, but the switching control complexity increases

Engineering Contradiction:

Improvepower consumptionVSAvoidswitching control complexity

Core Design Contradiction:

Loss of energyVSDevice complexity

Solution Approach 1:

The patent introduces switching circuits as intermediary components that manage the connection between the shared memory circuit and multiple arithmetic circuits. These switching circuits act as mediators that receive weight data from the memory and selectively route it to the appropriate arithmetic circuit based on control signals. This intermediary mechanism simplifies the overall control logic by centralizing the switching function in dedicated circuits rather than requiring complex distributed control logic across all components.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS20230297339A1Semiconductor device

Publication Date: 2023.09.21 SEMICON ENERGY LAB CO LTD

AI summary

A semiconductor device with a novel structure is provided. A first memory circuit portion includes a first memory circuit for retaining a plurality of pieces of first weight data. A second memory circuit portion includes a second memory circuit for retaining a plurality of pieces of second weight data. A first arithmetic circuit portion includes a first arithmetic circuit, a first switching circuit, and a third switching circuit. A second arithmetic circuit portion includes a second arithmetic circuit, a second switching circuit, and a fourth switching circuit. The first switching circuit has a function of supplying any one of the plurality of pieces of the first weight data to a first wiring. The second switching circuit has a function of supplying any one of the plurality of pieces of the second weight data to a second wiring. The third switching circuit has a function of supplying to the first arithmetic circuit the first weight data supplied to the first wiring or the second weight data supplied to the second wiring. The fourth switching circuit has a function of supplying to the second arithmetic circuit the first weight data supplied to the first wiring or the second weight data supplied to the second wiring.