Semiconductor Contact Terminals with Shared Solder Joints
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Solution Overview
Problem
Semiconductor chips face challenges in achieving high density contact terminals without increasing the risk of failure due to reduced pitch, which can lead to solder shorts and opens, and existing non-orthogonal arrangements are costly and restrict metal trace routing.
Innovation Solution
The semiconductor chip design allows for a minimum distance between contact terminals with some groups having a pitch less than the defined minimum, utilizing shared solder joints to increase density while mitigating failure risks through electrical or functional redundancy and error correction schemes, and employing shared solder joints to connect closely spaced terminals for increased reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the pitch between adjacent contact terminals is reduced to increase I/O density, then the contact terminal density increases, but the risk of solder shorts between adjacent interconnects increases
Solution Approach 1:
The patent segments contact terminals into different functional categories (signal terminals, power terminals, ground terminals) and applies different pitch rules to each category. Signal terminals maintain the minimum pitch to prevent shorts, while power and ground terminals can be placed closer together since they are electrically common. This segmentation allows higher overall density while maintaining reliability for critical signal connections.
Solution Approach 2:
The patent applies different pitch requirements to different locations and types of contact terminals based on their electrical function. Rather than applying a uniform minimum pitch across all terminals, the design allows localized variations where power and ground terminals have relaxed spacing requirements compared to signal terminals, optimizing both density and reliability locally.
2Reliability
If redundancy is applied to I/O signals to reduce failure risk, then the reliability increases, but the chip size must increase
Solution Approach 1:
The patent merges multiple contact terminals that share common electrical functions (power, ground) into groups that can be placed closer together. By combining these functionally similar terminals and allowing them to share the same electrical network, the design achieves redundancy and reliability without proportionally increasing chip area, as the merged groups occupy less space than individually spaced terminals would require.
3Quantity of substance
If a non-orthogonal chip I/O arrangement such as hexagonal arrangement is used to provide denser I/O, then the I/O density increases, but chip and substrate metal trace routing is restricted
Solution Approach 1:
The patent employs an asymmetric arrangement where signal terminals are positioned with minimum spacing in all directions to facilitate routing, while power and ground terminals are arranged in asymmetric groups that can be placed closer together. This asymmetric positioning strategy optimizes both routing accessibility and density, avoiding the symmetry constraints of hexagonal arrangements.
Data Source
AI summary
A semiconductor chip includes a semiconductor body having an active device region, one or more metallization layers insulated from the semiconductor body and configured to carry one or more of ground, power and signals to the active device region, and a plurality of contact terminals formed in or disposed on an outermost one of the metallization layers and configured to provide external electrical access to the semiconductor chip. A minimum distance between adjacent ones of the contact terminals is defined for the semiconductor chip. One or more groups of adjacent ones of the contact terminals have an electrical or functional commonality and a pitch less than the defined minimum distance. A single shared solder joint can connect two or more of the contact terminals of the semiconductor chip to one or more of contact terminals of a substrate such as a circuit board, an interposer or another semiconductor chip.