Semiconductor Device Shared Terminal Voltage Distribution

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Solution Overview

Problem

It is challenging to supply a uniform voltage to each semiconductor chip in a stacked semiconductor device as the number of chips increases, leading to voltage drops and non-uniform voltage distribution.

Innovation Solution

A semiconductor device design featuring a shared terminal connected to multiple semiconductor chips through through electrodes, with a first conductor on the top surface and a second conductor on the base member, using a connection wire to reduce internal resistance and ensure uniform voltage supply across all chips.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the number of stacked semiconductor chips is increased, then the functionality and integration of the device is improved, but voltage uniformity across chips deteriorates due to increased internal resistance

Engineering Contradiction:
Improvenumber of stacked semiconductor chipsVSAvoidvoltage uniformity
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The power supply path is segmented into multiple independent conductors (first conductor connected to top surface, second conductor connected to bottom surface) rather than relying on a single path through the stacked chips. This segmentation allows voltage to be supplied from both ends of the stack, reducing the effective resistance each chip experiences and improving voltage uniformity across all chips.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from a one-dimensional vertical power supply path (through the stack) to a three-dimensional power distribution network by adding conductors at both the top and bottom surfaces of the stack. This dimensional expansion creates multiple parallel current paths, reducing internal resistance and improving voltage uniformity while maintaining the ability to stack many chips.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If conventional power supply methods are used with increased chip stacking, then device integration is improved, but voltage drops increase due to internal resistance

Engineering Contradiction:
Improvedevice integrationVSAvoidvoltage drops
Core Design Contradiction:
ProductivityVSLoss of energy

Solution Approach 1:

The patent merges multiple power supply paths by connecting both the top surface (first conductor) and bottom surface (second conductor) of the stacked body to the power supply. This combining of parallel current paths reduces the total internal resistance of the power distribution network, thereby reducing voltage drops and energy losses while supporting higher chip stacking density.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design effectively reduces voltage drops and ensures that semiconductor chips receive voltage within a prescribed range, even with a larger number of stacked chips, by using a shared terminal and conductors to distribute power efficiently.

Implementation Method 1

a connection conductor connecting the first conductor and the second conductor... use a shared terminal and conductors to distribute power efficiently... reduces voltage drops

Methodology Applied
Scientific EffectElectrical Conduction: Conduction (electrical)

Data Source

PatentUS10593649B2Semiconductor device
Publication Date: 2020.03.17 KIOXIA CORP
  • US10593649B2 patent drawing
  • US10593649B2 patent drawing
  • US10593649B2 patent drawing

AI summary

A semiconductor device includes a base member, a stacked body on the base member, a first conductor on the stacked body, a second conductor on a top surface of the base member, and a connection conductor connecting the first conductor and the second conductor. The stacked body includes semiconductor chips stacked and a shared terminal connected to the plurality of semiconductor chips. The plurality of semiconductor chips each includes a functional element on a front surface side thereof and a through electrode extending from a back surface to the front surface side. The shared terminal has a top end positioned at a top surface of the stacked body and a bottom end positioned at a bottom surface of the stacked body. The first conductor is connected to the top end of the shared terminal, and the second conductor is electrically connected to the bottom end of the shared terminal.