Semiconductor Integrated Circuit Shared Timing Duty Adjusting

The patent applies universality by making the timing adjusting circuit and duty adjusting circuit serve dual purposes. The timing adjusting circuit adjusts timing for both DQS output (write operation) and REB output (read operation), while the duty adjusting circuit adjusts duty ratios for both signal types. This multi-functional design eliminates the need for separate circuits for each signal path, thereby reducing circuit area and leakage current while maintaining full timing adjustment capability for both write and read operations.

The patent reduces power consumption by implementing universal timing and duty adjusting circuits that handle both DQS and REB signal adjustments. Instead of maintaining separate active circuits for write and read operations, the shared circuits are activated only when needed, reducing static power consumption and leakage current while preserving the ability to adjust timing for both operation types.

The patent achieves downsizing by implementing universal timing and duty adjusting circuits that serve both DQS output and REB output functions. This approach reduces the total circuit area compared to having separate dedicated circuits for each signal path. The apparent complexity is managed through controlled switching between different operational modes (write mode with DQS output, read mode with REB output), allowing the same hardware resources to be reused efficiently.