Semiconductor Device Shared Transfer Path for Write Leveling
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Solution Overview
Problem
Semiconductor devices face challenges in maintaining high data transfer rates and bandwidth due to the degradation of tDQSS characteristics and increased area and number of input/output lines, particularly in sharing transfer paths for write and write leveling operations.
Innovation Solution
A semiconductor device design that shares a transfer path for write and write leveling operations, utilizing an input clock generation circuit, write leveling control circuit, and signal transfer circuit to generate and manage clocks and transfer signals, thereby preventing tDQSS degradation and reducing the number of input/output lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate transfer paths are provided for write operation and write leveling operation, then reliability of signal transfer is improved, but device area and number of input/output lines increase
Solution Approach 1:
The patent merges the transfer path for write operation and write leveling operation into a single shared transfer path. The signal transfer circuit selectively transfers either input clocks for write operation or write clocks for write leveling operation through the same transfer path, thereby reducing device area and number of input/output lines while maintaining signal transfer reliability through selective activation based on operation mode
Solution Approach 2:
The patent implements dynamic switching of the transfer path function based on operation mode. The signal transfer circuit dynamically selects which clocks to transfer (input clocks or write clocks) and adjusts transfer timing according to whether the device is performing write operation or write leveling operation, enabling a single transfer path to serve multiple functions without degradation of performance
2Stability of the object's composition
If separate transfer paths are provided for write operation and write leveling operation, then signal transfer stability is improved, but number of input/output lines increases
Solution Approach 1:
The patent combines multiple transfer paths into one shared transfer path that handles both write operation signals and write leveling operation signals. The signal transfer circuit ensures stable transfer by selectively activating the appropriate clock transfer function based on the current operation mode, thereby reducing the number of input/output lines while maintaining signal transfer stability
Solution Approach 2:
The signal transfer circuit is designed with multi-functionality to handle both write operation and write leveling operation through the same transfer path. It universally transfers different types of clocks (input clocks or write clocks) depending on the operation mode, reducing device complexity while ensuring stable signal transfer for all functions
3Manufacturing precision
If different transfer paths are used for write and write leveling operations, then tDQSS characteristic is maintained, but device area increases
Solution Approach 1:
The patent merges transfer paths while preserving tDQSS characteristics by carefully controlling the transfer timing and phase relationships. The signal transfer circuit maintains the required phase differences between clocks during write leveling operation even though they share the same physical transfer path, thereby preventing tDQSS degradation while reducing device area
Solution Approach 2:
The patent dynamically adjusts the transfer characteristics of the shared transfer path based on operation mode. During write leveling operation, the circuit ensures proper phase relationships are maintained to preserve tDQSS characteristics, while during write operation, it transfers input clocks with appropriate timing, thereby maintaining manufacturing precision requirements with a single transfer path
Data Source
AI summary
A semiconductor device includes an input clock generation circuit able to shift a write command in synchronization with a clock, and generating first and second input clocks. The semiconductor device also includes a write leveling control circuit able to divide a frequency of the clock in response to a write leveling control signal, and generating first to fourth write clocks. The semiconductor device includes a signal transfer circuit able to transfer the first and second input clocks as first and second transfer clocks in a write operation, and transferring the first to fourth write clocks as first to fourth transfer clocks in a write leveling operation.