Semiconductor Device Shared Well Power Rail Architecture
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
There is a need to reduce the area of integrated circuits (ICs) such as System-on-Chip (SoC) used in mobile devices while improving their performance and cell efficiency, particularly in semiconductor devices.
Innovation Solution
A semiconductor device design that includes power rails and wells with specific voltage configurations, allowing cells to share a common well and utilize different voltage levels, reducing the need for dummy regions and minimizing the overall area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple separate wells are provided for different voltage levels, then each cell can have dedicated voltage supply, but the device area increases due to repeated well structures and dummy regions
Solution Approach 1:
The patent merges multiple separate wells into a single shared well structure that serves multiple voltage levels (first voltage, second voltage, and third voltage) simultaneously. This single well is positioned between power rails and provides voltage supply to multiple cells through shared connections, eliminating the need for separate wells and dummy regions for each voltage level, thereby reducing overall device area while maintaining reliable voltage supply.
Solution Approach 2:
The single well structure is designed to perform multiple functions: it provides different voltage levels (first voltage from first power rail, second voltage from second power rail, and third voltage from third power rail) to multiple cells simultaneously. This multi-functional well replaces what would traditionally require multiple dedicated wells, achieving area reduction without compromising voltage supply reliability.
2Reliability
If cells are placed in separate regions with individual wells, then each cell has dedicated voltage supply, but metal wiring complexity and area increase
Solution Approach 1:
The patent combines multiple voltage supply paths into a single shared well structure. Instead of having separate metal wiring connections from power rails to individual wells for each cell, the single well receives connections from multiple power rails (first, second, and third power rails) and distributes voltages to multiple cells, significantly simplifying the metal wiring network.
Solution Approach 2:
The invention extracts and eliminates the redundant well structures and associated dummy regions that would be required for each voltage level. By removing these unnecessary repeated structures and replacing them with a single shared well, the metal wiring complexity is reduced while maintaining adequate voltage supply to all cells.
3Reliability
If dummy regions are added to isolate wells, then voltage isolation is improved, but the overall device area increases
Solution Approach 1:
The patent removes the need for dummy regions by eliminating the repeated well structures that would require isolation. Since multiple cells share a single well instead of having separate wells, the dummy regions used for isolating adjacent wells become unnecessary, thereby reducing device area while maintaining proper voltage isolation through the shared well architecture.
Solution Approach 2:
By merging multiple wells into a single shared well structure, the invention eliminates the boundaries between wells that would require dummy region isolation. The single well serves all cells, removing the need for isolation structures between wells and reducing overall device area.
Data Source
AI summary
A semiconductor device includes first, second, and third power rails extending in a first direction on a substrate and sequentially spaced apart in a second direction intersecting the first direction. A fourth power rail extends in the first direction on the substrate between the first and third power rails. A first well of a first conductive type is displaced inside the substrate between the first and third power rails. Cells are continuously displaced between the first and third power rails and share the first well. The first and third power rails are provided with a first voltage, the second power rail is provided with a second voltage different from the first voltage, the fourth power rail is provided with a third voltage different from the first voltage and the second voltage, and the cells are provided with the third voltage from the fourth power rail.