Semiconductor Shelf Region for Optical Access

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Solution Overview

Problem

Existing semiconductor device wire bond pads use planar technology, resulting in bond wires protruding above the top layer, which impedes full areal access for optics and reduces the active area-to-substrate surface area ratio, particularly in light detection applications where maximizing light-detection area is crucial.

Innovation Solution

A semiconductor device design featuring a shelf region between the top and bottom planar surfaces, with a wire attach pad located on the shelf, allowing the bond wire to be completely or partially below the top surface, thereby reducing the height of the bond wire above the die and enabling full surface access by optics.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If planar wire bond pad technology is used, then electrical connections can be established, but bond wires protrude above the top layer impeding optical access and reducing active area ratio

Engineering Contradiction:
Improveelectrical connection reliabilityVSAvoidactive area to substrate surface area ratio
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The invention transitions from a planar (2D) wire bond pad configuration to a three-dimensional structure by forming a recess in the substrate. The wire bond pad is positioned at the bottom of the recess, allowing bond wires to extend horizontally along the recess walls rather than protruding vertically above the surface. This dimensional change enables full optical access to the top surface while maintaining reliable electrical connections through the vertical recess structure.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If bond wires extend above the top surface, then electrical connections are established, but full areal access for optics is impeded

Engineering Contradiction:
Improveelectrical connection reliabilityVSAvoidoptical access
Core Design Contradiction:
ReliabilityVSEase of operation

Solution Approach 1:

The recess structure relocates the wire bond pad to a lower vertical dimension, allowing bond wires to traverse horizontally within the recess rather than extending above the top surface. This enables optics to access the full top areal surface without obstruction from protruding wires, while electrical connections remain reliable through the vertical recess pathway.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The wire bond pad and bond wires are nested within the recess structure, which is itself embedded in the substrate. This nesting arrangement conceals the electrical connection components within the substrate volume, keeping them out of the way of optical elements that require unobstructed access to the top surface.

Inventive Principle:
Principle #7Nested doll (Nesting)

3Productivity

If chips are packed closely to maximize light detection area, then light detection efficiency improves, but wire bonding area requirements conflict with active area

Engineering Contradiction:
Improvelight detection efficiencyVSAvoidwire bonding area
Core Design Contradiction:
ProductivityVSArea of stationary object

Solution Approach 1:

By positioning the wire bond pad at the bottom of a recess and allowing bond wires to extend horizontally along the recess walls, the invention effectively removes wire bonding area requirements from the top surface plane. This enables chips to be packed as closely as possible with maximum active area, while wire bonding occurs in the vertical recess space that would otherwise be part of the active detection volume.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design enhances the active area-to-substrate surface area ratio, allowing for closer packing of light detectors and improved light detection efficiency while maintaining mechanical stability and reducing package thickness.

Implementation Method 1

the wire is attached at both ends using some combination of heat, pressure, and/or ultrasonic energy to make a weld

Methodology Applied
Scientific EffectUltrasonic welding: Ultrasonic Vibration

Data Source

PatentUS9117721B1Reduced thickness and reduced footprint semiconductor packaging
Publication Date: 2015.08.25 EXCELITAS CANADA INC
  • US9117721B1 patent drawing
  • US9117721B1 patent drawing
  • US9117721B1 patent drawing

AI summary

Semiconductor devices and methods for forming semiconductor devices are presented. A device formed of a semiconductor material is configured to mount upon a substrate layer surface having a substrate layer wire attach pad. The device includes a top planar surface with an electrically active region, and a bottom planar surface disposed substantially parallel to the top planar surface. A shelf region is disposed between the top planar surface and the bottom planar surface, and a device wire attach pad in electrical communication with the active region is located on the shelf region.