Semiconductor Shielding Structure for Parasitic MOS Protection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor devices, parasitic MOS transistors can malfunction due to high potentials from wiring layers, leading to device malfunctions, especially when low-voltage and high-voltage transistors are integrated on a single substrate, causing reliability issues.
Innovation Solution
A semiconductor device design incorporating a second shield layer set at a potential lower than the wiring layer potential, reducing the effects of high potentials and preventing parasitic MOS transistor operation by enclosing the transistor formation region with a guard ring and offset insulating layer, and positioning the second shield layer between the gate electrode edges and the first shield layer edges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If low-voltage and high-voltage transistors are integrated on a single substrate, then the size of the semiconductor device is reduced, but parasitic MOS transistors may operate due to high potential from wiring layers, causing device malfunction
Solution Approach 1:
A guard ring region is introduced as an intermediary structure between the high-voltage transistor and the parasitic MOS transistor. The guard ring is electrically connected to a low potential (ground or negative potential) and acts as a mediator to prevent the high potential from the wiring layer from activating the parasitic MOS transistor, thus resolving the reliability issue while maintaining device integration
Solution Approach 2:
The offset insulating layer is formed in advance in the transistor formation region before the parasitic MOS transistor can be activated by high potential. This preliminary protective structure prevents the harmful effect of high potential from reaching and activating the parasitic transistor, thereby maintaining device reliability in the integrated configuration
2Reliability
If shield layers are added to prevent parasitic MOS transistor activation, then device reliability is improved, but device complexity increases
Solution Approach 1:
The guard ring region serves multiple functions: it acts as a shield to prevent parasitic MOS transistor activation, provides a reference potential for the transistor formation region, and can be integrated with existing device structures. This multi-functionality reduces the need for additional separate protective structures, thereby limiting the increase in device complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the reliability of semiconductor devices by preventing parasitic MOS transistor activation, thus avoiding malfunctions and increasing the layout flexibility of the wiring layer, while maintaining a specific potential distribution that shields against high voltage effects.
Implementation Method 1
the second shield layer is provided in at least part of a first region and/or at least part of a second region, the first region being a region between one edge of the gate electrode and an edge of the first shield layer opposite to the edge of the gate electrode in the channel width direction when viewed from the top side
Data Source
AI summary
A semiconductor device including: a semiconductor layer; a gate insulating layer; a gate electrode; a channel region; a source region and a drain region; a guard ring region; an offset insulating layer; a first interlayer dielectric; a first shield layer formed above the first interlayer dielectric and the guard ring region and electrically connected to the guard ring region; a second interlayer dielectric; and a second shield layer formed above the second interlayer dielectric, wherein the first shield layer is provided outside of both ends of the gate electrode in a channel width direction when viewed from the top side; and wherein the second shield layer is provided in at least part of a first region and/or at least part of a second region, the first region being a region between one edge of the gate electrode and an edge of the first shield layer opposite to the edge of the gate electrode in the channel width direction when viewed from the top side, and the second region being a region between the other edge of the gate electrode and an edge of the first shield layer opposite to the other edge of the gate electrode in the channel width direction when viewed from the top side.