Semiconductor Device Shielding Against Mold Interface Charges
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Solution Overview
Problem
Semiconductor devices with superjunction transistor arrangements are vulnerable to interface charges induced by mold materials, which can impair their functionality and blocking capability.
Innovation Solution
A semiconductor device design featuring a layer stack with alternating first and second doping type semiconductor layers, accompanied by additional semiconductor regions and a thick third semiconductor layer that extends between these regions, acts as a shielding structure to mitigate the impact of interface charges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional transistor arrangement with drift regions and compensation regions is used, then the device can achieve basic switching functionality, but the device is vulnerable to interface charges from mold material that impair blocking capability
Solution Approach 1:
A third semiconductor layer is introduced as an intermediary between the mold material and the drift regions. This layer acts as a mediator that prevents direct interaction between interface charges and the sensitive drift regions, thereby protecting the blocking capability while maintaining switching functionality.
Solution Approach 2:
The solution adds a vertical dimension to the device structure by inserting a third semiconductor layer between the mold material and the drift regions. This dimensional addition creates a physical barrier that separates the harmful interface charges from the functional regions, resolving the vulnerability without compromising device performance.
2Reliability
If additional semiconductor layers and regions are added to protect against interface charges, then robustness against interface charges improves, but device complexity increases
Solution Approach 1:
The third semiconductor layer serves multiple functions simultaneously: it provides mechanical support, acts as an electrical barrier against interface charges, and maintains structural integrity. This multi-functionality allows the device to achieve enhanced robustness without proportionally increasing complexity.
Solution Approach 2:
The thickness of the third semiconductor layer is optimized to be at least twice the sum of the drift region thickness and compensation region thickness. This parameter specification ensures adequate protection against interface charges while controlling the overall device complexity through defined dimensional relationships.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design enhances the robustness of semiconductor devices against interface charges, maintaining or improving their blocking capability while minimizing the impact of unwanted charges on the device's operation.
Implementation Method 1
A third semiconductor region of a first doping type or a second doping type is formed such that the third semiconductor region extends from a first surface into a first region of the third semiconductor layer
Data Source
AI summary
A semiconductor device includes a layer stack with a plurality of first semiconductor layers of a first doping type and a plurality of second semiconductor layers of a second doping type complementary to the first doping type. A first semiconductor region of a first semiconductor device adjoins the first semiconductor layers. Each second semiconductor region of the first semiconductor device adjoins at least one of the second semiconductor layers, and is spaced apart from the first semiconductor region. A third semiconductor layer adjoins the layer stack and each first semiconductor region and each second semiconductor region. The third semiconductor layer includes a first region arranged between the first semiconductor region and the second semiconductor region in a first direction. A third semiconductor region of the first or the second doping type extends from a first surface of the third semiconductor layer into the first region.