Semiconductor Shielding Structures for Thermal Stress Management
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Solution Overview
Problem
Existing semiconductor device packaging structures are unsatisfactory as they fail to adequately manage thermal stress between semiconductor devices and substrates with different coefficients of thermal expansion, leading to cracks and device failures, especially in larger packages.
Innovation Solution
A semiconductor device package design featuring a redistribution layer with a top metal layer or contact pad that shields stress, preventing cracks from propagating through layers, and a method for determining contact pad deployment to balance stress relief and metal routing needs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the device package size is increased, then the productivity and functionality are improved, but thermal stress and crack propagation increase due to CTE mismatch
Solution Approach 1:
The patent applies local quality by creating a graded CTE structure where the intermediate layer has a CTE that transitions between the semiconductor device and substrate. This localized property variation allows the large device package to accommodate thermal expansion differences without cracking, resolving the contradiction between size and reliability.
Solution Approach 2:
The patent uses composite materials by introducing an intermediate layer with specific CTE properties between the semiconductor device and substrate. This composite structure combines materials with different CTEs to create a transition zone that absorbs thermal stress, enabling larger packages to maintain reliability.
2Ease of manufacture
If wire bonding is used for connections, then ease of manufacture is improved, but device complexity and space requirements increase
Solution Approach 1:
The patent extracts the wire bonding process entirely by implementing direct bump bonding between the semiconductor device and substrate. This removal of the wire bonding step simplifies the package structure and reduces complexity while maintaining ease of manufacture through direct electrical and mechanical connection.
Solution Approach 2:
The patent inverts the traditional connection approach by flipping the semiconductor device and using bump structures that protrude from the device surface for direct bonding. This inversion eliminates the need for wire bonds and creates a more compact, less complex package structure.
3Reliability
If passivation layers are added to protect integrated circuits, then reliability is improved, but stress management and crack propagation control worsen
Solution Approach 1:
The patent introduces an intermediate layer as a mediator between the passivation layer and substrate. This intermediate layer acts as a stress buffer that protects the passivation layer from excessive stress concentration while maintaining the protective function, thus resolving the contradiction between protection and stress management.
Solution Approach 2:
The patent changes the CTE parameter of the intermediate layer to create a gradual transition from the low CTE of the semiconductor device to the higher CTE of the substrate. This parameter variation allows the passivation layer to remain protective while reducing stress concentration and preventing crack propagation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively reduces stress on devices, prevents cracks, and maintains adequate metal routing, enhancing the reliability and performance of semiconductor device packages, particularly for larger sizes exceeding 500 mm2.
Implementation Method 1
the contact pad is large enough to shield stress from the passive device and prevent cracks from reaching the passive device
Data Source
AI summary
Semiconductor device packages and method are provided. A semiconductor device package according to the present disclosure includes a substrate including a first region, a passive device disposed over the first region of the substrate, a contact pad disposed over the passive device, a passivation layer disposed over the contact pad, a recess through the passivation layer, and an under-bump metallization (UBM) layer. The recess exposes the contact pad and the UBM layer includes an upper portion disposed over the passivation layer and a lower portion disposed over a sidewall of the recess. A projection of the upper portion of the UBM layer along a direction perpendicular to the substrate falls within an area of the contact pad.