Semiconductor Package Shunt Capacitor Reducing Parasitic Inductance
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Solution Overview
Problem
The characteristics of semiconductor devices with a quad flat package (QFP) structure are affected by parasitic inductance and resistance from leads and wiring patterns on the Printed Circuit Board (PCB), leading to deteriorated decoupling and electromagnetic compatibility (EMC) characteristics.
Innovation Solution
Incorporating a capacitor with electrodes formed on both sides of a base substrate, connected to a semiconductor substrate and lead, within the semiconductor package, which stabilizes the capacitor's position relative to the semiconductor chip, reducing the impact of PCB wiring patterns on device characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the capacitor is provided outside the package on the PCB, then the number of components inside the package is reduced, but the decoupling characteristics deteriorate due to parasitic inductance and resistance from leads and wiring patterns
Solution Approach 1:
The patent merges the capacitor component with the base substrate by forming capacitor electrodes directly on the base substrate surface. This integration eliminates the need for separate capacitor components and their connecting leads, thereby reducing device complexity while simultaneously improving decoupling characteristics by minimizing parasitic inductance and resistance.
Solution Approach 2:
The patent utilizes the surface area of the base substrate as a mounting plane for the capacitor electrodes, effectively using the two-dimensional surface of the base substrate to host additional circuit elements. This approach allows the capacitor to be formed within the package footprint without increasing the number of discrete components, resolving the contradiction between component integration and performance.
2Device complexity
If the capacitor is mounted on the PCB outside the package, then the package structure remains simple, but the EMC characteristics vary due to the wiring pattern on the PCB
Solution Approach 1:
By integrating the capacitor electrodes directly onto the base substrate, the patent eliminates the external wiring patterns on the PCB that cause EMC variations. The capacitor becomes an intrinsic part of the package structure, maintaining simplicity while ensuring stable EMC characteristics independent of PCB layout.
3Ease of operation
If leads and wiring patterns on PCB are used to connect the capacitor, then the capacitor can be placed outside the package, but parasitic inductance and resistance increase
Solution Approach 1:
The patent transitions from three-dimensional external component mounting to two-dimensional integration on the base substrate surface. The capacitor electrodes are formed directly on the base substrate, eliminating the need for vertical leads and external wiring patterns, thereby minimizing parasitic inductance and resistance while maintaining design flexibility.
Data Source
AI summary
A semiconductor device has a package structure provided with leads that are external connection terminals. A base substance is an island, and at least the surface thereof is formed of a conductive material. A semiconductor substrate is mounted on the surface of the base substance, and a ground potential is supplied from the surface of the base substance. A shunt capacitor is provided with an electrode pair of a first electrode and a second electrode formed in parallel, and mounted with the first electrode being electrically connected to the surface of the base substance. An internal bonding wire connects a pad provided on the semiconductor substrate for external connection, to the second electrode of the shunt capacitor. The lead is the external connection terminal of the semiconductor device. An external bonding wire connects the lead to the second electrode of the shunt capacitor.