Semiconductor Devices With Silicon-Germanium Layers

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Solution Overview

Problem

As semiconductor devices shrink, their operation uniformity degrades, necessitating improved mismatch characteristics to enhance reliability and resistance to external environments in analog circuits.

Innovation Solution

The design includes a substrate with distinct regions for high and low voltage transistors, where the high voltage transistors feature a silicon-germanium layer and a capping layer with specific impurity concentrations and depths for source/drain regions, while low voltage transistors do not, and the manufacturing method involves epitaxial growth of these layers and regions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of moving object

If the size of the semiconductor device is reduced, then the integration density is improved, but the operation uniformity of the analog circuit is degraded

Engineering Contradiction:
Improvedevice sizeVSAvoidoperation uniformity
Core Design Contradiction:
Area of moving objectVSReliability

Solution Approach 1:

The patent applies local quality by creating distinct regions within the semiconductor device: a first region with a silicon-germanium layer for high-voltage transistors and a second region without it for low-voltage transistors. This allows different areas to have optimized characteristics for their specific functions, maintaining operation uniformity in analog circuits while enabling size reduction through integrated high-voltage capability.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The semiconductor device is segmented into multiple functional regions with different structures. The first region contains a silicon-germanium layer between the substrate and gate electrode for high-voltage operation, while the second region lacks this layer for low-voltage operation. This segmentation enables the device to accommodate both high-voltage and low-voltage transistors in a compact structure, improving integration density without compromising analog circuit uniformity.

Inventive Principle:
Principle #1Segmentation

2Reliability

If a silicon-germanium layer is added to high voltage transistors, then the voltage withstand capability is improved, but the device complexity is increased

Engineering Contradiction:
Improvevoltage withstand capabilityVSAvoidlayer structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The silicon-germanium layer is selectively applied only to the first region where high-voltage transistors are formed, while the second region for low-voltage transistors remains without this layer. This segmented approach provides the necessary voltage withstand capability for high-voltage operation without unnecessarily increasing the complexity of low-voltage device structures.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The silicon-germanium layer is introduced locally in the first region to provide high-voltage capability where needed, rather than applying it uniformly across the entire device. This local modification improves voltage withstand capability for high-voltage transistors while minimizing the increase in overall device complexity.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach improves the reliability and uniformity of semiconductor devices by reducing characteristic variations between transistors, enhancing their operational stability and resistance to environmental factors.

Implementation Method 1

the manufacturing method involves epitaxial growth of these layers and regions

Methodology Applied
Scientific EffectEpitaxial growth: Epitaxy

Data Source

PatentUS9825033B2Semiconductor devices and methods of manufacturing the same
Publication Date: 2017.11.21 SAMSUNG ELECTRONICS CO LTD
  • US9825033B2 patent drawing
  • US9825033B2 patent drawing
  • US9825033B2 patent drawing

AI summary

An integrated circuit device includes a substrate including a first region and a second region, a first transistor in the first region, the first transistor being an N-type transistor and including a first silicon-germanium layer on the substrate, and a first gate electrode on the first silicon-germanium layer, and a second transistor in the second region and including a second gate electrode, the second transistor not having a silicon-germanium layer between the substrate and the second gate electrode.