Semiconductor Side Face Angling for Crack Prevention
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Solution Overview
Problem
Semiconductor devices using Wafer Level Chip Size Package (W-CSP) technology face challenges with moisture absorption and thermal cycling-induced cracks due to the exposure of interlayer insulation films and differences in thermal expansion coefficients between materials.
Innovation Solution
A semiconductor device structure and manufacturing method that involves forming a first insulator on the side face of the semiconductor substrate with a plane direction angled between −5° and +5° relative to the main face, and using a second insulator with a specific profile to cover the side face, which helps dissipate stress and prevent cracks during thermal cycling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the interlayer insulation film is exposed at the package side face after dicing, then the manufacturing process is simplified, but moisture resistance deteriorates
Solution Approach 1:
The patent applies composite materials by forming a silane-based coating film over the exposed interlayer insulation film at the package side face. This coating film combines the structural properties of the underlying oxidized silicon film with the moisture-resistant properties of the silane-based material, creating a composite structure that maintains both manufacturing simplicity and moisture resistance.
Solution Approach 2:
The silane-based coating film acts as an intermediary layer between the exposed interlayer insulation film and the external environment. This intermediate coating provides the moisture barrier function without requiring changes to the underlying interlayer insulation film structure or additional complex manufacturing steps.
2Ease of manufacture
If dicing is performed after forming the sealing resin, then the manufacturing process is simplified, but thermal cycling-induced cracks occur due to stress concentration
Solution Approach 1:
The patent changes the physical-chemical parameters of the package side face by forming a silane-based coating film that modifies the surface properties. This parameter change reduces the coefficient of thermal expansion mismatch and stress concentration at the dicing line, preventing crack formation during thermal cycling while maintaining the simplified manufacturing process.
Solution Approach 2:
The silane-based coating film is formed beforehand on the package side face to provide stress relief and crack prevention. This preparatory coating cushions against the thermal stresses that will occur during subsequent thermal cycling, preventing the initiation and propagation of cracks at the dicing lines.
3Ease of manufacture
If a conventional dicing blade is used, then the manufacturing process is simple, but the scribe line width is too wide for high-density chip production
Solution Approach 1:
The patent replaces the purely mechanical dicing action with a combined chemical-mechanical approach. A silane-based coating film is first deposited chemically onto the package side face, providing a protective and stress-relief layer. This allows subsequent dicing with finer blades to produce narrower scribe lines without compromising structural integrity, enabling higher chip production density.
Data Source
AI summary
A semiconductor device having a structure that can reduce stress due to difference in coefficients of thermal expansion and prevent or suppress generation of cracks, and a semiconductor device manufacturing method, are provided. The semiconductor device includes a single crystal silicon substrate having a main face on which semiconductor elements are formed and a side face intersecting with the main face, and a sealing resin provided covering at least a portion of the side face. The side face covered by the sealing resin is equipped with a first face with a plane direction forming an angle of −5° to +5° to the plane direction of the main face.