Semiconductor Package Side Surface Metal Layer for Solder Inspection
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Solution Overview
Problem
Conventional wafer level packages face issues with solder bridging and solder joint defects due to excessive solder and narrow separation between I/O pads and saw scribe lane areas, making it difficult to inspect solder joints for defects and increasing the risk of short circuits.
Innovation Solution
A semiconductor device with a metal layer extending to and covering the side surfaces of a package body, optionally made of copper and coated with a wettable material like tin, which exposes electrical contacts for improved solder joint visibility and reduces the risk of flux residues or solder flakes causing short circuits by encapsulating the die on all sides with a molding material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the I/O pad is positioned close to the saw scribe lane area to reduce package size, then the device footprint is reduced, but the risk of solder bridging and short circuits increases due to flux residue or solder flakes
Solution Approach 1:
The package structure is segmented into distinct functional zones: the I/O pad area, the saw scribe lane area, and a newly introduced passivation overlap area that acts as a protective buffer zone between them. This segmentation prevents direct contact between solder and sensitive areas, reducing short circuit risk while maintaining compact dimensions.
Solution Approach 2:
The passivation overlap area serves as an intermediary protective barrier between the I/O pad and saw scribe lane. This intermediate zone captures and contains flux residue and solder flakes, preventing them from bridging the I/O pad and causing short circuits, thus enabling closer pad placement without compromising reliability.
2Area of stationary object
If the I/O pad does not extend to the sides of the WLP to maintain compact structure, then the device remains small, but solder joint inspection becomes difficult after mounting
Solution Approach 1:
The I/O pad structure is extended from a traditional bottom-only configuration to include vertical extension along the side surfaces of the package body. This three-dimensional configuration allows solder joints to be accessible from multiple directions, enabling inspection from the side even when the pad does not extend to the peripheral edges of the package bottom surface.
Solution Approach 2:
The metal layer is configured to extend onto the side surface of the package body in advance, creating a visible inspection surface before mounting. This preliminary configuration of the electrical contact structure allows for pre-mounting inspection and post-mounting verification of solder joints from the side, eliminating the need for pad extension to the package edges.
3Reliability
If excessive solder is used to ensure reliable electrical connection, then electrical performance is improved, but solder bridging and flux residue problems worsen
Solution Approach 1:
The passivation overlap area is selectively positioned only in the critical region where solder flakes and flux residue are most likely to migrate - between the I/O pad and saw scribe lane. This localized quality enhancement provides targeted protection against solder bridging without requiring changes to the overall soldering process or excessive solder restriction, maintaining reliable electrical connections while containing harmful factors.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances solder joint inspection and reduces the likelihood of short circuits by providing wettable flanks for solder joints and protecting the semiconductor die on six sides, allowing for improved electrical performance and reduced package height without the need for a die carrier or mount.
Implementation Method 1
the metal layer may comprise copper and the metal layer may be coated with a wettable material, such as tin
Implementation Method 2
a molding material encapsulating the top major surface, the bottom major surface and the side surfaces of the semiconductor die
Data Source
AI summary
A semiconductor device structure and method of manufacturing a semiconductor device. The semiconductor device may comprise a semiconductor die having a top major surface that has one or more electrical contacts formed thereon, an opposing bottom major surface, and side surfaces; a molding material encapsulating the top major surface, the bottom major surface and the side surfaces of the semiconductor die, wherein the molding material defines a package body that has a top surface and a side surface; wherein the plurality of electrical contacts are exposed on the top surface of the package body and a metal layer is arranged over and electrically connected to the electrical contacts and wherein the metal layer extends to and at least partially covers a side surface of the package body.