Semiconductor Package Side Surface Connection Terminals
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Solution Overview
Problem
Conventional wafer level packages face challenges in increasing the number of connection terminals while maintaining reliability and cost-effectiveness, as the redistribution of metal wiring layers increases fabrication costs and reduces the adhesion of solder balls, limiting the arrangement of solder balls on the semiconductor chip.
Innovation Solution
The solution involves arranging connection terminals on the side surfaces of a semiconductor package, with conductive pads exposed through openings in an insulating layer, and using reinforcing members to support these terminals, allowing for a higher density of connection terminals without increasing the semiconductor chip size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If solder balls are reduced in size to increase the number of connection terminals, then the number of connection terminals increases, but the adhesion of solder balls to the underlying metal pad weakens
Solution Approach 1:
The patent transitions from arranging connection terminals only on the top surface to utilizing the side surfaces of the package as well. This dimensional expansion allows more connection terminals to be arranged without reducing their size, thereby maintaining adhesion strength while increasing the total number of terminals.
Solution Approach 2:
The patent divides the connection terminal arrangement into different spatial zones: top surface terminals and side surface terminals. This segmentation allows the top surface terminals to maintain larger sizes for good adhesion, while the side surface terminals provide additional connection points, resolving the contradiction between quantity and adhesion.
2Reliability
If metal wiring layer is redistributed on the semiconductor chip, then electrical connection is achieved, but fabrication cost increases and reliability degrades due to separation from chip surface
Solution Approach 1:
The patent extracts the metal wiring layer redistribution step from the fabrication process. Instead of redistributing metal wiring on the chip surface, the invention uses the original pad layout directly and forms connection terminals on both top and side surfaces, eliminating the costly and reliability-degrading redistribution process.
Solution Approach 2:
Instead of redistributing metal wiring to achieve electrical connections (conventional approach), the patent inverts the approach by maintaining the original metal pad positions and achieving electrical connections through side surface exposure and direct terminal formation, thereby simplifying the process and improving reliability.
3Quantity of substance
If connection terminals are arranged on side surface of semiconductor package, then the number of connection terminals increases and pitch is reduced, but structural support and protection become more challenging
Solution Approach 1:
The patent merges the structural support function with the insulating layer and reinforcing members. The insulating layer not only electrically isolates the side surface terminals but also provides structural support, while reinforcing members embedded in the insulating layer further strengthen the side surface structure, combining multiple functions into integrated components.
Solution Approach 2:
The patent uses composite structures combining insulating materials with reinforcing members (such as metal meshes or structural supports) to create a side surface structure that provides both electrical insulation and mechanical strength, enabling the arrangement of numerous side surface terminals without compromising structural integrity.
Data Source
AI summary
Provided are a semiconductor package having connection terminals whose side surfaces are exposed and a semiconductor module including such a semiconductor package. Also provided are methods of fabricating the semiconductor package and semiconductor module. According to an embodiment of the present invention, a semiconductor package includes a semiconductor chip including a semiconductor wafer having first and second opposite surfaces and a plurality of conductive pads arranged in a row on the first surface along the edges of the semiconductor wafer such that a side surface of each conductive pad is exposed. An insulating layer is formed on the first surface of the semiconductor wafer and includes openings for exposing parts of the conductive pads. A plurality of connection terminals are respectively arranged on the conductive pads exposed through the openings and a reinforcing member is arranged on the insulating layer to cover a portion of each connection terminal.


