Semiconductor Patterning via Sidewall Image Transfer
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Solution Overview
Problem
Conventional semiconductor patterning processes face challenges in achieving smaller, more densely packed features due to limitations in overlay accuracy and resolution, necessitating the development of improved methods for forming semiconductor structures.
Innovation Solution
A self-aligned double patterning (SADP) process using a sidewall image transfer (SIT) technique, where alternately arranged spacers and mandrels form masks to pattern a target layer, allowing for the formation of semiconductor structures with enlarged dimensions and uniform, denser layouts by utilizing unetched mandrel and spacer portions as masks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional single patterning process is used, then the process is simple, but the feature size cannot be reduced further due to lithographic limits
Solution Approach 1:
The patterning process is segmented into multiple steps: first forming mandrels with initial dimensions, then forming spacers on the mandrels, and finally using the combined mandrel-spacer structure as a mask for pattern transfer. This segmentation allows the final feature dimensions to be determined by the spacer thickness rather than being limited by single-step lithographic resolution
Solution Approach 2:
The invention transitions from two-dimensional planar patterning to three-dimensional structured patterning by forming vertical spacers on mandrels. The spacer height dimension provides an additional degree of freedom for controlling final pattern dimensions, enabling feature sizes below the lithographic resolution limit through vertical spacer thickness control rather than horizontal lithographic patterning
2Quantity of substance
If feature sizes are decreased to increase device density, then device density improves, but overlay accuracy and resolution requirements exceed lithographic capabilities
Solution Approach 1:
The spacers are formed through self-aligned deposition on the mandrels, automatically positioning themselves with precise alignment to the mandrel structures. This self-alignment mechanism eliminates the need for additional overlay operations, achieving sub-lithographic dimensions without requiring superimposed lithographic patterns and their associated overlay accuracy challenges
3Manufacturing precision
If conventional patterning is used to form dense patterns, then the process flow is simple, but the achievable pitch is limited by lithographic resolution
Solution Approach 1:
Mandrels are formed in advance with dimensions and positions that will ultimately determine the pitch of the final patterns. The spacers are then deposited on these pre-formed mandrels, inheriting their pitch arrangement. This preliminary formation of mandrels with target pitch allows the final pattern pitch to be defined by the spacer thickness rather than requiring direct lithographic patterning at the target pitch
Data Source
AI summary
The present invention provides a method of forming a semiconductor structure including the following steps. Firstly, a target layer is formed on a substrate, and a plurality of mandrels is formed on the target layer. Next, a material layer is formed on the target layer to cover the mandrels. Then, an etching process is performed to partially remove each of the mandrel and the material layer covered on each mandrel, to form a plurality of mask. Finally, the target layer is patterned through the masks, to form a plurality of patterns. Through the present invention, each mask comprises an unetched portion of each mandrel and a spacer portion of the material covered on each mandrel, and a dimension of each of the patterns is larger than a dimension of each of the mandrel.