Semiconductor RDL Sidewall Isolation for Singulation Crack Control

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Solution Overview

Problem

The miniaturization of semiconductor devices leads to increased complexity in manufacturing, resulting in issues such as inaccurate component placement, poor electrical interconnections, crack development, delamination, and high yield loss, which complicates the modification of semiconductor structures and increases manufacturing costs.

Innovation Solution

A semiconductor structure with a substrate, redistribution layer (RDL), conductive bump, and an isolation layer is implemented, where the isolation layer is disposed over the sidewall to fill and seal recesses formed during the singulation process, thereby minimizing crack propagation and enhancing the reliability of the semiconductor structure.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If semiconductor devices are miniaturized to reduce size, then device size is reduced, but manufacturing complexity increases and reliability deteriorates

Engineering Contradiction:
Improvedevice sizeVSAvoidmanufacturing reliability
Core Design Contradiction:
Volume of moving objectVSReliability

Solution Approach 1:

The isolation layer is applied to the sidewall before the final singulation cut is made. This preliminary action prevents cracks from propagating into the device during the cutting process, thereby maintaining reliability even as device size is reduced

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The isolation layer acts as an intermediary material between the sidewall and the cutting tool. It absorbs the mechanical stress and prevents direct transmission of cutting forces to the device structure, thus preventing crack formation during miniaturization

Inventive Principle:
Principle #24Intermediary (Mediator)

2Manufacturing precision

If more manufacturing steps are implemented to handle complexity, then manufacturing precision may improve, but device complexity increases and yield loss increases

Engineering Contradiction:
Improvecomponent placement precisionVSAvoidmanufacturing process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The crack prevention function is extracted from the main device structure and implemented as a separate isolation layer. This allows crack prevention to be addressed independently without complicating the core device design or manufacturing process

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The isolation layer is applied locally only to the sidewall region where cracks are most likely to form during cutting. This localized approach prevents unnecessary complexity in other parts of the device while maintaining manufacturing precision

Inventive Principle:
Principle #3Local quality

3Adaptability or versatility

If manufacturing operations are increased to assemble more components, then device functionality is improved, but material wastage increases and manufacturing cost increases

Engineering Contradiction:
Improvedevice functionalityVSAvoidmaterial wastage
Core Design Contradiction:
Adaptability or versatilityVSLoss of substance

Solution Approach 1:

The isolation layer provides beforehand cushioning to the sidewall, preventing crack formation that would lead to device failure and material wastage. This protective measure ensures that more devices survive the manufacturing process, reducing yield loss

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentUS11798860B2Semiconductor structure and manufacturing method thereof
Publication Date: 2023.10.24 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11798860B2 patent drawing
  • US11798860B2 patent drawing
  • US11798860B2 patent drawing

AI summary

A semiconductor structure includes a substrate comprising a die pad disposed over the substrate, and a passivation disposed over the substrate and surrounding the die pad, a redistribution layer (RDL) comprising a dielectric layer disposed over the passivation and an interconnect structure disposed within the dielectric layer and electrically connecting with the die pad, a conductive bump disposed over and electrically connected with the interconnect structure; and an isolation layer surrounding the substrate and the RDL.