Semiconductor Package Sidewall Profile to Reduce Saw Chipping

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Solution Overview

Problem

Existing semiconductor manufacturing processes face challenges in ensuring the reliability and integrity of semiconductor devices during the wafer sawing and packaging stages, particularly due to the potential for chipping and damage to the semiconductor components during cutting, which can affect the electrical connections and overall performance.

Innovation Solution

A method involving controlled cutting processes with specific blade sizes and profiles to minimize sidewall damage, combined with a step-form profile of the substrate sidewalls and the use of insulating materials to enhance bonding strength and protect the semiconductor devices, ensuring reliable electrical connections and improved heat dissipation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional wafer sawing and packaging processes are used, then manufacturing efficiency is maintained, but sidewall chipping and damage occur during cutting

Engineering Contradiction:
Improvesidewall integrityVSAvoidmanufacturing efficiency
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The substrate is divided into multiple semiconductor devices with trenches formed between them, allowing individual processing and packaging of each device while maintaining overall manufacturing efficiency. The segmentation enables precise control of sidewalls during cutting operations.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Trenches are formed in the substrate before the wafer sawing process to define precise cutting paths and protect sidewalls. This preliminary structuring prevents chipping during subsequent cutting operations while maintaining manufacturing flow.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If standard cutting processes are used, then manufacturing speed is maintained, but mechanical strength and reliability deteriorate due to sidewall damage

Engineering Contradiction:
Improvedevice reliabilityVSAvoidmanufacturing speed
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

Insulating materials are deposited on the sidewalls of trenches and substrates before packaging to cushion and protect against mechanical damage during wafer sawing and handling. This protective layer prevents chipping and enhances sidewall strength without slowing production.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Solution Approach 2:

The substrate structure combines semiconductor material with insulating materials formed on sidewalls, creating a composite structure that maintains mechanical strength during processing while enabling reliable electrical connections in the final device.

Inventive Principle:
Principle #40Composite materials

3Reliability

If insulating materials are added to protect sidewalls, then reliability improves, but device complexity increases

Engineering Contradiction:
Improveelectrical connectivityVSAvoidprocess complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The insulating materials serve multiple functions: protecting sidewalls during manufacturing, providing electrical isolation between devices, and facilitating reliable bonding during packaging. This multi-functionality reduces the need for additional specialized components or processes.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The formation of insulating materials is merged with the existing packaging process flow, combining protective functionality with electrical isolation requirements in a single integrated process sequence rather than adding separate steps.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS20250210437A1Semiconductor device, semiconductor package, and methods of manufacturing the same
Publication Date: 2025.06.26 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250210437A1 patent drawing
  • US20250210437A1 patent drawing
  • US20250210437A1 patent drawing

AI summary

A semiconductor device includes a substrate, an interconnect structure, and conductive vias. The substrate has a first side, a second side and a sidewall connecting the first side and the second side, wherein the sidewall includes a first planar sidewall of a first portion of the substrate, a second planar sidewall of a second portion of the substrate and a curved sidewall of a third portion of the substrate, where the first planar sidewall is connected to the second planar sidewall through the curved sidewall. The interconnect structure is located on the first side of the substrate, where a sidewall of the interconnect structure is offset from the second planar sidewall. The conductive vias are located on the interconnect structure, where the interconnect structure is located between the conductive vias and the substrate.