Semiconductor Patterning Using Sidewall Spacer Etching
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Solution Overview
Problem
Current photolithography tools struggle to achieve sufficient resolution and efficient reduction in feature size and pitch for semiconductor devices, leading to increased costs and time in device fabrication, as the development cycle for next-generation devices outpaces the improvement in tool resolution capabilities.
Innovation Solution
A method involving a series of photolithography and etching processes, including the use of hard mask layers and sidewall spacer elements, to form patterns with reduced dimensions, allowing for precise control and reduction of critical dimensions in semiconductor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photolithography tools are used to fabricate semiconductor devices, then device fabrication can be performed, but the minimum feature size and pitch cannot be sufficiently reduced due to resolution limitations
Solution Approach 1:
The patent applies segmentation by dividing the single photolithography exposure step into multiple sequential exposure steps (e.g., LELE - lithography-etch-lithography-etch, or multiple patterning steps). Each exposure step forms a portion of the final pattern, allowing the overall pitch to be reduced below the resolution limit of individual exposure steps. The first exposure forms initial patterns, subsequent exposures add additional patterns, and etching steps transfer these patterns through multiple layers, achieving fine pitch features that would be impossible with a single exposure.
2Manufacturing precision
If immersion lithography tools are used to increase resolution capabilities, then feature size reduction is achieved, but the time to market increases and development cycle is extended
Solution Approach 1:
The patent uses multiple standard photolithography exposure steps instead of requiring advanced immersion lithography tools. By segmenting the patterning into sequential exposures and etching steps, the method achieves fine pitch using existing tooling, avoiding the long lead times associated with immersion lithography tool development and deployment.
Solution Approach 2:
The patent performs preliminary patterning actions in sequential steps. The first exposure and etching step prepares the substrate with initial patterns and modified regions, which then serve as the basis for subsequent exposures. This preliminary action allows later steps to build upon established patterns, achieving complex fine-pitch structures through manageable sequential operations rather than requiring advanced single-step lithography.
3Manufacturing precision
If multiple photolithography and etching processes are used to reduce critical dimensions, then pattern size is reduced, but process complexity increases
Solution Approach 1:
The patent merges multiple patterning operations into an integrated process flow where exposure, etching, and spacer formation steps are combined to achieve the final pattern. Rather than treating each step as separate, the process is designed so that each step contributes to and enables the next, with shared process parameters and equipment. This merging reduces the operational complexity compared to performing truly separate, independent patterning operations.
Data Source
AI summary
The present disclosure provides a method including providing a semiconductor substrate and forming a first layer and a second layer on the semiconductor substrate. The first layer is patterned to provide a first element, a second element, and a space interposing the first and second elements. Spacer elements are then formed on the sidewalls on the first and second elements of the first layer. Subsequently, the second layer is etched using the spacer elements and the first and second elements as a masking element.